公开(公告)号：EP1956615A3

公开(公告)日：2008-12-24

申请号：EP07254736.7

申请日：2007-12-07

Applicant: Renesas Technology Corp.

Inventor： Takahashi, Wataru ,  Tsuchida, Shigeru ,  Okabe, Hiroshi

IPC: H01F17/00 ,  H05K1/02 ,  H05K1/16 ,  H04B1/38 ,  H01L23/48 ,  H01L23/52 ,  H01L23/64

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns (MS21,MS22,MS23,MS24) each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node (Nin) and the other thereof is set to a signal output node (Nout). Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

公开(公告)号：EP1956615A2

公开(公告)日：2008-08-13

申请号：EP07254736.7

申请日：2007-12-07

Applicant: Renesas Technology Corp.

Inventor： Takahashi, Wataru ,  Tsuchida, Shigeru ,  Okabe, Hiroshi

IPC: H01F17/00 ,  H05K1/02 ,  H05K1/16 ,  H04B1/38 ,  H01L23/48 ,  H01L23/52 ,  H01L23/64

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node and the other thereof is set to a signal output node. Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

Abstract translation: 通过层叠至少具有电感元件的第一至第四布线图案来实现并联谐振电路。 相邻的第一布线图案和第二布线图案中的一个被设置为信号输入节点，另一个被设置为信号输出节点。 然后，信号输入节点依次经由第一布线图案，第三布线图案，第四布线图案和第二布线图案的电感元件连接到信号输出节点。 通过相邻地形成信号输入和输出节点的布线层，与分离时相比，输入和输出节点之间的电容值增加。 而且，通过增加第一布线图案和第二布线图案的线宽，可以进一步增加电容值。 因此，可以实现小面积的大电容值和电子设备的小型化。