公开(公告)号：WO2013052329A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/057301

申请日：2012-09-26

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： NGUYEN, Qui Vi ,  ARIKI, Takuya ,  PARK, Jongmin

IPC: G11C8/08 ,  G11C16/08

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/12

Abstract: A level shifter circuit is presented that can apply a negative voltage level (VBB at TrFG) to non-selected blocks while still being able to drive a high positive level (VRDEC) when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device (M9, M10) whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs (M9, M10) are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

Abstract translation: 提出了一种电平移位器电路，其可以在未选择的块上施加负电压电平（VBB，TrFG），同时在选择时仍能够驱动高电平（VRDEC）。 一个示例性实施例提出了不易受低电压pfet击穿影响的负电平转换器。 这允许可以为未选择的块驱动负电平的高电压电平移位器（传输门），并且当被选择的块被使能时，仍然可以驱动正的高电压电平。 通过使用一对在设计中n阱与其他PMOS晶体管具有相同电平的低电压PMOS器件（M9，M10），布局面积可以最小化。 这对PMOS（M9，M10）的栅极连接到VSS，从而防止这些低电压PMOS器件发生薄氧化物击穿。