公开(公告)号：WO2016032706A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/043728

申请日：2015-08-05

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LU, Ching-Huang ,  DONG, Yingda ,  PANG, Liang ,  KUO, Tien-Chien

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3404 ,  G11C16/3459

Abstract: Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programing pass (801) in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied (807) to control gates of the memory cells. Subsequently, a final programming pass is performed (808) in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programing pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.

Abstract translation: 提供了在编程电荷俘获存储器单元时减少短期电荷损失的影响的技术。 短时间的电荷损失可导致降档和阈值电压分布的扩大。 编程操作包括对于每个目标数据状态，将存储器单元编程为接近最终阈值电压分布的粗略编程遍（801）。 随后，施加负电压（807）以控制存储器单元的栅极。 随后，执行最终编程遍（808），其中将存储器单元编程为最终阈值电压分布。 由于负电压加速电荷损失，因此在最终编程通过后电荷损失减小。 粗略编程通过可以使用增量步进脉冲编程来获得最低目标数据状态，以获得关于编程速度的信息。 可以根据编程速度设置最终编程遍历中的初始编程电压。

公开(公告)号：WO2016057158A1

公开(公告)日：2016-04-14

申请号：PCT/US2015/049510

申请日：2015-09-10

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： KUO, Tien-Chien ,  KOH, Yee Lih

IPC: G11C7/10 ,  G11C11/56

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5622 ,  G11C2211/5633

Abstract: A flash memory allows a range of charges to be programmed into its cells to represent 8 distinct memory states, which are encoded by 3 bits (upper, middle, lower) of data. A page of memory cells which is programmed or read in parallel yields corresponding upper, middle and lower data pages. In page-by-page schemes, each data page can be programmed and read independently. Each data page has a predetermined set of read points to distinguish between"1" and "0" bits. Prior state encodings have to use different sets of read points for a lower data page depending on whether or not the higher data pages are already programmed, as indicated by maintaining a flag. The present programming and state encoding schemes have invariant read points, independent of the program status of the higher order pages and do not require maintaining a flag, thereby improving read performance.

Abstract translation: 闪存允许将一系列电荷编程到其单元中以表示8个不同的存储器状态，其由3位（上，中，下）数据编码。 并行编程或读取的一页存储单元产生相应的上，中和下数据页。 在逐页方案中，每个数据页可以独立编程和读取。 每个数据页都具有一组预定的读点以区分“1”和“0”位。 先决状态编码必须根据是否已经编程较高的数据页面，为较低的数据页使用不同的读取点集，如通过维持标志所指示的。 目前的编程和状态编码方案具有不变读取点，与高阶页面的程序状态无关，并且不需要维护标志，从而提高读取性能。

公开(公告)号：WO2014025513A1

公开(公告)日：2014-02-13

申请号：PCT/US2013/051364

申请日：2013-07-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： KUO, Tien-Chien ,  HUYNH, Jonathan Hoang ,  WANG, Sung-En

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/34

Abstract: In a nonvolatile memory array that stores randomized data, the program level - the number of states per cell stored in a population of memory cells - is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.

Abstract translation: 在存储随机化数据的非易失性存储器阵列中，程序级别 - 存储在存储器单元群中的每个存储单元的状态数量是从在读取条件下通过存储器单元群的总电流确定的， 线，例如NAND闪存中的源线。

公开(公告)号：WO2012177368A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/040145

申请日：2012-05-31

Applicant: SANDISK TECHNOLOGIES INC. ,  LIU, Bo ,  PARK, Jongmin ,  CHEN, Chen ,  KUO, Tien-Chien

Inventor： LIU, Bo ,  PARK, Jongmin ,  CHEN, Chen ,  KUO, Tien-Chien

IPC: G11C29/40 ,  G11C29/44

CPC classification number: G11C29/40 ,  G11C29/44

Abstract: A circuit (150) for counting in an N-bit string (10) a number of bits M, having a first binary value includes N latch circuits in a daisy chain (100) where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to "interrogate" any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from "no-pass" to "pass" state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

Abstract translation: 用于以N位串（10）计数具有第一二进制值的位M的电路（150）包括菊花链（100）中的N个锁存电路，其中每个锁存电路具有一个标签位， 要么是没有通过，要么是通过状态。 最初，标签位根据N位串的位进行设置，其中第一个二进制值对应于无通状态。 具有脉冲串的时钟信号通过菊花链运行以“询问”任何无通路锁存电路。 它可以通过任何通过锁存电路进行比赛。 然而，对于无通路锁存电路，被阻塞的前导脉冲也在标签位从“无通”状态到“通过”状态的脉冲周期之后复位，以允许随后的脉冲通过。 在所有无通路锁存电路复位之后，M由脉冲序列的丢失脉冲数给出。

公开(公告)号：EP2893535A1

公开(公告)日：2015-07-15

申请号：EP13730442.4

申请日：2013-06-07

Applicant: SanDisk Technologies Inc.

Inventor： SAKAI, Manabu ,  MIWA, Toru ,  KUO, Tien-Chien

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5621

Abstract: Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.

公开(公告)号：EP2883228A1

公开(公告)日：2015-06-17

申请号：EP13745938.4

申请日：2013-07-19

Applicant: SanDisk Technologies Inc.

Inventor： PAN, Feng ,  KUO, Tien-Chien ,  WAN, Jun ,  LEI, Bo

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/34

Abstract: In a nonvolatile memory array that stores randomized data, the program level - the number of states per cell stored in a population of memory cells - may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.

公开(公告)号：WO2016048609A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048045

申请日：2015-09-02

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LEE, Juan Carlos ,  NGUYEN, Hao Thai ,  MUI, Man Lung ,  KUO, Tien-Chien ,  MIZUTANI, Yuki

IPC: G11C7/12 ,  G11C7/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C7/12 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26

Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Abstract translation: 在NAND闪存中，位线预充/放电时间可以是确定程序，擦除和读取性能的主要组成部分。 在常规布置中，位线电平由感测放大器设置，位线通过读出放大器路径被放电到源极线电平。 在这种布置下，基于位线的RC常数，预充电/放电时间由远端（相对于感测放大器）支配。 因此，减少位线预充电/放电时间，从而提高了NAND​​闪存的性能，从而提高了整体系统的性能。 为了解决这个问题，通过使用虚拟NAND串将额外的路径引入到公共源级的位线之间。 在基于示例性3D-NAND（BiCS）的实施例中，虚拟NAND串从虚拟块中获取，其中虚拟块可以被放置在整个阵列中以均匀分布放电电流。

公开(公告)号：WO2016025167A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/042504

申请日：2015-07-28

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： KOH, Yee Lih ,  KUO, Tien-Chien ,  MUI, Man Lung ,  LEE, Juan Carlos

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.

Abstract translation: 在写入多状态非易失性存储器时，编程周期中包含解除捕获操作。 为了降低包括解除捕获操作的性能损失，与验证操作交替的单个增加脉冲序列的编程周期被包括来自两个或多个楼梯中的每一个的脉冲的周期替换，其中每个阶梯用于相应的 数据状态的子集。 在多个脉冲之后，但在进行以下验证之前，在编程周期中插入解除捕获操作。

公开(公告)号：WO2014039129A1

公开(公告)日：2014-03-13

申请号：PCT/US2013/044846

申请日：2013-06-07

Applicant: SANDISK TECHNOLOGIES, INC. ,  SAKAI, Manabu ,  MIWA, Toru ,  KUO, Tien-Chien

Inventor： SAKAI, Manabu ,  MIWA, Toru ,  KUO, Tien-Chien

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5621

Abstract: Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.

Abstract translation: 提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。 最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。 这两组锁存器也可用于在该程序数据的编程期间存储验证状态。 可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。 例如，上页数据可以最初存储在一组锁存器中。 当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。 如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

公开(公告)号：WO2014025512A1

公开(公告)日：2014-02-13

申请号：PCT/US2013/051359

申请日：2013-07-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： PAN, Feng ,  KUO, Tien-Chien ,  WAN, Jun ,  LEI, Bo

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/34

Abstract: In a nonvolatile memory array that stores randomized data, the program level - the number of states per cell stored in a population of memory cells - may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.

Abstract translation: 在存储随机数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级别 - 存储在存储器单元群中的每个存储单元的状态数量。 用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。