公开(公告)号：WO2014025513A1

公开(公告)日：2014-02-13

申请号：PCT/US2013/051364

申请日：2013-07-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： KUO, Tien-Chien ,  HUYNH, Jonathan Hoang ,  WANG, Sung-En

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/34

Abstract: In a nonvolatile memory array that stores randomized data, the program level - the number of states per cell stored in a population of memory cells - is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.

Abstract translation: 在存储随机化数据的非易失性存储器阵列中，程序级别 - 存储在存储器单元群中的每个存储单元的状态数量是从在读取条件下通过存储器单元群的总电流确定的， 线，例如NAND闪存中的源线。

公开(公告)号：WO2013103504A1

公开(公告)日：2013-07-11

申请号：PCT/US2012/069817

申请日：2012-12-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： NGUYEN, Hao Thai ,  LEE, Juan Carlos ,  LEE, Seungpil ,  MATSUMOTO, Masahide ,  PARK, Jongmin ,  MUI, Man Lung ,  WANG, Sung-En

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit lines, and, optionally, the well can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit lines can be equalized to a DC level. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening verify, the source and bit line levels can be left to float.

Abstract translation: 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 考虑脉冲和验证阶段之间的间隔。 对于脉冲之后的间隔，但是在建立验证条件之前，可以使源极，位线和可选的阱均衡，然后在期望的DC电平进行调节。 在验证阶段之后，但是在为下一个脉冲施加偏置存储器之前，可以将源和位线均衡为直流电平。 在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。 在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前没有中间验证，源和位线电平可以保持浮动。