公开(公告)号：WO2015119973A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014319

申请日：2015-02-03

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： MATSUMOTO, Masahide ,  YAMASHITA, Ryuji

IPC: G11C7/04 ,  G01K7/01 ,  G01K15/00

CPC classification number: G01K15/005 ,  G01K7/00 ,  G01K7/01 ,  G01K13/00 ,  G01K2215/00 ,  G01K2219/00 ,  G05F3/245 ,  G11C7/04 ,  G11C16/06 ,  H03M1/12 ,  H03M1/38 ,  H03M7/165

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Abstract translation: 温度传感器电路具有可在两个温度下调节的参考电压发生器，以提高精度。 参考电压产生部分产生可调整电平的参考电压。 连接分压器部分以从参考电压产生部分接收参考电压，并产生由参考电压和可调整电阻确定的多个比较电压电平。 然后可以将模数转换器连接到依赖于温度的电压部分，以接收与温度相关的输出电压，例如与绝对温度类型（PTAT）的比例，并连接到分压器部分以接收比较电压 水平。 基于与温度相关的输出电压与比较电压电平的比较，模数转换器产生指示温度的输出。

公开(公告)号：WO2013103504A1

公开(公告)日：2013-07-11

申请号：PCT/US2012/069817

申请日：2012-12-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： NGUYEN, Hao Thai ,  LEE, Juan Carlos ,  LEE, Seungpil ,  MATSUMOTO, Masahide ,  PARK, Jongmin ,  MUI, Man Lung ,  WANG, Sung-En

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit lines, and, optionally, the well can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit lines can be equalized to a DC level. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening verify, the source and bit line levels can be left to float.

Abstract translation: 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 考虑脉冲和验证阶段之间的间隔。 对于脉冲之后的间隔，但是在建立验证条件之前，可以使源极，位线和可选的阱均衡，然后在期望的DC电平进行调节。 在验证阶段之后，但是在为下一个脉冲施加偏置存储器之前，可以将源和位线均衡为直流电平。 在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。 在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前没有中间验证，源和位线电平可以保持浮动。