公开(公告)号：JPH1027485A

公开(公告)日：1998-01-27

申请号：JP5951997

申请日：1997-03-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

IPC: G11C16/02 ,  G11C7/10 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To decrease the number of connecting lines connected between the one side of a pad and the other side of a pad of a memory device to reduce an area of a device. SOLUTION: A non-volatile memory device comprises an internal bus 3, a timer 8, and an enable/disable circuit 5 for enabling and disabling access to the internal bus. The timer 8 controls the internal bus, an enables transmitting an information signal of a memory device from a local auxiliary line on the internal bus 3 when the internal bus 3 is in an inactive period in a normal memory data reading cycle. The timer 8 controls an enable/disable means, and permits/negates access to the internal bus 3 by an information signal or data from/to a memory.

公开(公告)号：JPH1027492A

公开(公告)日：1998-01-27

申请号：JP5919297

申请日：1997-03-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

IPC: G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To simplify the architecture of a data input/output management device by reducing the number of data transmission lines necessary for a memory and concentrating information thereof in a single point. SOLUTION: This device includes the following equipment and elements. That is, internal busses 1H and 1L for data transmission to a memory or from the memory are provided at least one bi-direction, and a redundant management line 2 transmits redundancy data associatively with the internal busses 1H and 1L. Switches 5L, 6L, 5H and 5L enable/unable the internal busses 1H and 1L to transmit data from the memory to the outside. A switch 9 enables/unables an external source to access the internal busses for data transmission to a memory matrix, and switches 8L. and 8H enable/unable the outside of the memory and a redundant line 2 to be connected during reading of the memory matrix or its programming.

公开(公告)号：JPH1027488A

公开(公告)日：1998-01-27

申请号：JP7546997

申请日：1997-03-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

IPC: G11C16/06 ,  G11C7/14 ,  G11C16/28

Abstract: PROBLEM TO BE SOLVED: To enable adapting to a nonvolatile storage having less numbers of reference lines and particularly provided with a hierarchical decoder by providing the reference line and a data propagation/reproducing circuit, etc. SOLUTION: This circuit is divided to half matrices of two memories, and is provided with the reference lines 3, 3' and additional propagation/delay reproducing lines 4, 4' for reproducing propagation of signals along the reference lines 3, 3' with regard to respective matrices. These respective unit lines are provided with the same structure as respective general word lines of a storage. One side reference lines and propagation/delay reproducing lines of the half matrices 2-4, 2'-4' of two memories can be activated when the memory cells of the other half matrix are selected. Then, the reference lines synchronous and symmetrical related to the selection of the memory cells are provided for the read-out, and conditions for starting the precise and sure read-out of the memory cells selected by that are preset by the propagation/delay reproducing line 4.

公开(公告)号：IT1291209B1

公开(公告)日：1998-12-29

申请号：ITTO970227

申请日：1997-03-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FONTANA MARCO ,  BARCELLA ANTONIO ,  MONTANARO MASSIMO ,  PAOLINO CARMELO

IPC: G11C16/26

Abstract: The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

公开(公告)号：ITTO970227A1

公开(公告)日：1998-09-18

申请号：ITTO970227

申请日：1997-03-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FONTANA MARCO ,  BARCELLA ANTONIO ,  MONTANARO MASSIMO ,  CARMELO PAOLINO

IPC: G11C16/26

Abstract: The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.