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    NON-VOLATILE MEMORY DEVICE AND DATA TRANSMITTING METHOD FOR NON-VOLATILE MEMORY DEVICE
    1.
    发明专利
    NON-VOLATILE MEMORY DEVICE AND DATA TRANSMITTING METHOD FOR NON-VOLATILE MEMORY DEVICE 失效

    公开(公告)号：JPH1027485A

    公开(公告)日：1998-01-27

    申请号：JP5951997

    申请日：1997-03-13

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

    IPC: G11C16/02 ,  G11C7/10 ,  G11C16/06

    Abstract: PROBLEM TO BE SOLVED: To decrease the number of connecting lines connected between the one side of a pad and the other side of a pad of a memory device to reduce an area of a device. SOLUTION: A non-volatile memory device comprises an internal bus 3, a timer 8, and an enable/disable circuit 5 for enabling and disabling access to the internal bus. The timer 8 controls the internal bus, an enables transmitting an information signal of a memory device from a local auxiliary line on the internal bus 3 when the internal bus 3 is in an inactive period in a normal memory data reading cycle. The timer 8 controls an enable/disable means, and permits/negates access to the internal bus 3 by an information signal or data from/to a memory.

    REFERENCE WORD LINE AND DATA PROPAGATION/REPRODUCING CIRCUIT FOR USING IN STORAGE, AND METHOD FOR READING OUT STORAGE
    3.
    发明专利
    REFERENCE WORD LINE AND DATA PROPAGATION/REPRODUCING CIRCUIT FOR USING IN STORAGE, AND METHOD FOR READING OUT STORAGE 失效

    公开(公告)号：JPH1027488A

    公开(公告)日：1998-01-27

    申请号：JP7546997

    申请日：1997-03-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

    IPC: G11C16/06 ,  G11C7/14 ,  G11C16/28

    Abstract: PROBLEM TO BE SOLVED: To enable adapting to a nonvolatile storage having less numbers of reference lines and particularly provided with a hierarchical decoder by providing the reference line and a data propagation/reproducing circuit, etc. SOLUTION: This circuit is divided to half matrices of two memories, and is provided with the reference lines 3, 3' and additional propagation/delay reproducing lines 4, 4' for reproducing propagation of signals along the reference lines 3, 3' with regard to respective matrices. These respective unit lines are provided with the same structure as respective general word lines of a storage. One side reference lines and propagation/delay reproducing lines of the half matrices 2-4, 2'-4' of two memories can be activated when the memory cells of the other half matrix are selected. Then, the reference lines synchronous and symmetrical related to the selection of the memory cells are provided for the read-out, and conditions for starting the precise and sure read-out of the memory cells selected by that are preset by the propagation/delay reproducing line 4.

    7.
    发明专利
    未知

    公开(公告)号：IT9020157D0

    公开(公告)日：1990-04-27

    申请号：IT2015790

    申请日：1990-04-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DALLAROBA MARCO ,  ROLANDI PAOLO ,  MACCALLI MARCO

    IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175 ,  H03K

    Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

    9.
    发明专利
    未知

    公开(公告)号：DE69126245T2

    公开(公告)日：1997-11-06

    申请号：DE69126245

    申请日：1991-06-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DALLABORA MARCO ,  ROLANDI PAOLO ,  MACCALLI MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28

    Abstract: The device comprises a source bias generator (4) suitable for conferring upon the EPROM cell (2) during the reading step a source voltage that varies linearly with the power supply voltage so as to keep constant the voltage between gate and source of the above cell (2).

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