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11 records (took 0.021 seconds)

    1.
    发明专利
    未知

    公开(公告)号：ITMI980639A1

    公开(公告)日：1999-09-27

    申请号：ITMI980639

    申请日：1998-03-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MULATTI JACOPO ,  BRANCHETTI MAURIZIO ,  COMMODARO STEFANO ,  GHILARDELLI ANDREA

    IPC: G11C16/30

    Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

    2.
    发明专利
    未知

    公开(公告)号：ITMI972883A1

    公开(公告)日：1999-06-29

    申请号：ITMI972883

    申请日：1997-12-29

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  COMMODARO STEFANO ,  LOMAZZI GUIDO

    IPC: G11C8/18 ,  G11C16/32

    Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

    3.
    发明专利
    未知

    公开(公告)号：IT1298817B1

    公开(公告)日：2000-02-02

    申请号：ITMI980639

    申请日：1998-03-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MULATTI JACOPO ,  BRANCHETTI MAURIZIO ,  COMMODARO STEFANO ,  GHILARDELLI ANDREA

    IPC: G11C16/30

    Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

    4.
    发明专利
    未知

    公开(公告)号：IT1296908B1

    公开(公告)日：1999-08-02

    申请号：ITMI972883

    申请日：1997-12-29

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  COMMODARO STEFANO ,  LOMAZZI GUIDO

    IPC: G11C8/18 ,  G11C16/32

    Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

    5.
    发明专利
    未知

    公开(公告)号：IT1296888B1

    公开(公告)日：1999-08-02

    申请号：ITMI972811

    申请日：1997-12-19

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： MACCARRONE MARCO ,  COMMODARO STEFANO ,  CARRERA MARCELLO ,  GHILARDELLI ANDREA

    IPC: G05F1/10 ,  G11C20060101

    Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

    Low-supply-voltage nonvolatile memory device with voltage boosting
    9.
    发明公开
    Low-supply-voltage nonvolatile memory device with voltage boosting 失效
    Versichungspnung和Spannungserhöher

    公开(公告)号：EP0814481A1

    公开(公告)日：1997-12-29

    申请号：EP96830345

    申请日：1996-06-18

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  COMMODARO STEFANO

    IPC: G11C16/08 ,  G11C16/06

    CPC classification number: G11C16/08

    Abstract: The memory device (1) has a plurality of local boost circuits (10), each connected to a sector (4) of the memory array (3), and each having a control circuit (10), at least a respective boost capacitor (13), and a respective drive circuit (16a, 16b). Each drive circuit is only enabled in read mode, on receiving signal ATD and a sector enabling signal (ENi), for reading memory cells (5) forming part of the respective sector (4a, 4b). The boost voltage (VBN) is only supplied to the final inverter (9) of the row decoder (7); a clamping diode (14) limits the boost voltage to prevent undesired direct biasing of the PMOS transistors (38) of the final inverters (9) connected to the nonaddressed word lines (6); and the overvoltage is therefore only supplied locally when and where necessary.

    Abstract translation: 存储器件（1）具有多个本地升压电路（10），每个局部升压电路（10）分别连接到存储器阵列（3）的扇区（4），并且每个具有控制电路（10），至少相应的升压电容器 13）和相应的驱动电路（16a，16b）。 每个驱动电路仅在读取模式下，在接收信号ATD和扇区使能信号（ENi）上被使能，用于读取形成相应扇区（4a，4b）的一部分的存储器单元（5）。 升压电压（VBN）仅提供给行解码器（7）的最终反相器（9）; 钳位二极管（14）限制升压电压以防止连接到非寻址字线（6）的最终反相器（9）的PMOS晶体管（38）的不期望的直接偏置; 因此只有当需要时才能在本地提供过电压。

    Nonvolatile memory with a single-cell reference signal generating circuit for reading memory cells
    10.
    发明公开
    Nonvolatile memory with a single-cell reference signal generating circuit for reading memory cells 失效
    与单细胞参考信号产生电路的非易失性存储器，用于读取的存储器单元

    公开(公告)号：EP0814484A1

    公开(公告)日：1997-12-29

    申请号：EP96830348

    申请日：1996-06-18

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  COMMODARO STEFANO

    IPC: G11C16/28 ,  G11C16/06

    CPC classification number: G11C16/28

    Abstract: A nonvolatile memory (35) presenting a data memory array (2) including memory cells 85); a read circuit (40) including a plurality of sense amplifiers (10), each connected to a respective array branch (17) to be connected to the memory cells; and a reference generating circuit (55) including a single reference cell (60) arranged outside the data memory array (2) and generating a reference signal (IR). The reference generating circuit (55) presents a plurality of reference branches (41), each connected to a respective sense amplifier (10); and current mirror circuits (53, 54, 62, 63) interposed between the reference cell (60) and the reference branches (41), and supplying the reference branches with the reference signal (IR).

    Abstract translation: 一种非易失性存储器（35）呈现数据存储器阵列（2）包括存储单元85）; 读出电路（40）包括读出放大器（10）多个，每一个连接到一个respectivement阵列分支（17）被连接到所述存储器单元; 和参考发生电路（55）包括数据存储器阵列（2），并产生一个参考信号（IR）以外布置在单个参考单元（60）。 参考发生电路（55）呈现的参考分支有多个（41），每个连接到一个respectivement读出放大器（10）; 和参考单元（60）和参考分支（41）和供给与所述参考信号（IR）的参考分支之间的电流镜电路（53，54，62，63）。

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