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公开(公告)号：ITMI972883A1
公开(公告)日：1999-06-29
申请号：ITMI972883
申请日：1997-12-29
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , COMMODARO STEFANO , LOMAZZI GUIDO
Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
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公开(公告)号：IT1298594B1
公开(公告)日：2000-01-12
申请号：ITMI980454
申请日：1998-03-06
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： MACCARRONE MARCO , LOMAZZI GUIDO , GHEZZI STEFANO , FERRARIO DONATO
Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.
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公开(公告)号：ITMI980454A1
公开(公告)日：1999-09-06
申请号：ITMI980454
申请日：1998-03-06
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： MACCARRONE MARCO , LOMAZZI GUIDO , GHEZZI STEFANO , FERRARIO DONATO
Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.
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公开(公告)号：IT1296908B1
公开(公告)日：1999-08-02
申请号：ITMI972883
申请日：1997-12-29
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , COMMODARO STEFANO , LOMAZZI GUIDO
Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
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