公开(公告)号：JP2540028B2

公开(公告)日：1996-10-02

申请号：JP32511294

申请日：1994-12-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

公开(公告)号：JPH07249299A

公开(公告)日：1995-09-26

申请号：JP32511294

申请日：1994-12-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To obtain an integrated programming circuit having redundancy by enabling the drive of a redundant programming load circuit according to the logical state of a data line through a switch circuit in response to a decoded output signal and inhibiting the drive of the other programming load circuit. CONSTITUTION: When a defective column address COLADD is supplied to a memory device, signals (OCO-OC3 and OCON-OC3N) are outputted from the identification code of a matrix part stored in a non-volatile register RR where this defective column address COLADD is stored. The output signals are supplied to a NAND gate 7 and in response to the output signal of the NAND gate 7, a switch circuit 6 enables the drive of a redundant programming load circuit PLOADR according to the logical state of a data line (DO-D15). At the same time, the gate 7 inhibits the drive of another programming load circuit (PLOADO-PLOAD15) through the switch circuit 6.

公开(公告)号：DE69321245D1

公开(公告)日：1998-10-29

申请号：DE69321245

申请日：1993-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).

公开(公告)号：IT1296888B1

公开(公告)日：1999-08-02

申请号：ITMI972811

申请日：1997-12-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MACCARRONE MARCO ,  COMMODARO STEFANO ,  CARRERA MARCELLO ,  GHILARDELLI ANDREA

IPC: G05F1/10 ,  G11C20060101

Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

公开(公告)号：ITMI972811A1

公开(公告)日：1999-06-21

申请号：ITMI972811

申请日：1997-12-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MACCARRONE MARCO ,  COMMODARO STEFANO ,  CARRERA MARCELLO ,  GHILARDELLI ANDREA

IPC: G05F1/10 ,  G11C20060101

公开(公告)号：DE69321245T2

公开(公告)日：1999-04-29

申请号：DE69321245

申请日：1993-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).

公开(公告)号：IT1298186B1

公开(公告)日：1999-12-20

申请号：ITMI980115

申请日：1998-01-23

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  MACCARRONE MARCO ,  BRANCHETTI MAURIZIO

IPC: G11C8/08 ,  H03K19/0185

Abstract: A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.

公开(公告)号：IT1298594B1

公开(公告)日：2000-01-12

申请号：ITMI980454

申请日：1998-03-06

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MACCARRONE MARCO ,  LOMAZZI GUIDO ,  GHEZZI STEFANO ,  FERRARIO DONATO

IPC: H03K21/00 ,  H03K23/00

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

公开(公告)号：ITMI980454A1

公开(公告)日：1999-09-06

申请号：ITMI980454

申请日：1998-03-06

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MACCARRONE MARCO ,  LOMAZZI GUIDO ,  GHEZZI STEFANO ,  FERRARIO DONATO

IPC: H03K21/00 ,  H03K23/00

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

公开(公告)号：DE69318842D1

公开(公告)日：1998-07-02

申请号：DE69318842

申请日：1993-12-02

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

IPC: G11C8/10 ,  G11C16/06 ,  G11C17/00 ,  G11C8/00

Abstract: A memory line decoding driver (1) is so biased that the P channel pull-up transistor (6) biasing the final inverter (5) conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage (18) alternatively connects the gate terminal of the pull-up transistor (6) to a capacitor (37), with which the charge is distributed, and to the supply (VPC).