公开(公告)号：JPH08288839A

公开(公告)日：1996-11-01

申请号：JP7824696

申请日：1996-03-06

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MERUKIOORE BURUTSUKORERI ,  JIYANFURANKO BUAI ,  SARUBATOORE PORUTARURI ,  MARUKO DEMICHIERI

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

Abstract: PROBLEM TO BE SOLVED: To provide a fully integral phase locked loop(PLL) circuit which can optimize short-term stable characteristics while minimizing jitter by effectively removing the interference of high frequency noises or the like. SOLUTION: Concerning the fully integral PLL circuit having improved jitter characteristics, a 3rd pole p3 is led into the transfer function of PLL circuit by connecting a capacitor between the output of voltage/current conversion input step at a voltage controlled oscillator(VCO) 14 and the common ground node of circuit. The value of that capacitor is controlled while utilizing the same digital/analog converter(DAC) to be ordinarily used for controlling the time constant of low-pass loop filter 13. Through such a method, the gap between zero and the 3rd pole p3 in a frequency domain is kept constant, a damping factor is not changed but kept constant and ω0 of PLL circuit is fluctuated (increased).

公开(公告)号：JPH0964729A

公开(公告)日：1997-03-07

申请号：JP35098695

申请日：1995-12-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MERUKIOORE BURUTSUKORERI ,  GAETANO KOSENTEINO ,  MARUKO DEMICHIERI ,  JIYUSETSUPE PATSUTEI

IPC: H03L7/093 ,  H03L7/089

Abstract: PROBLEM TO BE SOLVED: To obtain a highly precise differential charge pump circuit which can suppress a common mode error to a minimum and which can prevent the occurrence of common mode voltage fluctuation without a correction instruction. SOLUTION: Two same current sources Gb1 and Gb2 are connected to nodes A and B and they continuously inject current I to the nodes A and B. Two pairs of current sources Gc1 and Gc2 and Gc3 and Gc4, which are switch- controlled, are connected to the nodes A and B and they can pull in current I from the nodes to which the respective current sources are connected. The two current sources of the respective pairs of the current sources are controlled by one of a pair of control signals and the inverse signal of the other signal. Then, the whole two pairs of the current sources which are switch-controlled can be set to the same type (N type). Two current sources are set to the same type (P type) and they are controlled by a common mode feedback loop.

公开(公告)号：JPH08335880A

公开(公告)日：1996-12-17

申请号：JP14376496

申请日：1996-05-14

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MERUKIOORE BURUTSUKORERI ,  MARUKO DEMICHIERI ,  JIYUSETSUPE PATSUTEI ,  BUARERIO PISATEI

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed processable secondary digital/analog converter(DACQ) which does not increase current consumption but rather decreases current consumption. SOLUTION: A DACQ composed of a pair of serially connected 1st and 2nd linear converter (DAC) has direct coupling between the output node of 1st DAC 1 and the R-2R type resistor circuit network of 2nd DAC 2, corresponding to the LSB step of R-2R type resistor circuit. A high impedance node, especially the input node of 2nd DAC is appropriately removed from a current path, so as to significantly reduce the problem of comparatively long settling time at the high impedance node (having a related originally large parasitic capacitance). The circuit is markedly simplified by the special architecture of this DACQ.