公开(公告)号：JPH0964729A

公开(公告)日：1997-03-07

申请号：JP35098695

申请日：1995-12-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MERUKIOORE BURUTSUKORERI ,  GAETANO KOSENTEINO ,  MARUKO DEMICHIERI ,  JIYUSETSUPE PATSUTEI

IPC: H03L7/093 ,  H03L7/089

Abstract: PROBLEM TO BE SOLVED: To obtain a highly precise differential charge pump circuit which can suppress a common mode error to a minimum and which can prevent the occurrence of common mode voltage fluctuation without a correction instruction. SOLUTION: Two same current sources Gb1 and Gb2 are connected to nodes A and B and they continuously inject current I to the nodes A and B. Two pairs of current sources Gc1 and Gc2 and Gc3 and Gc4, which are switch- controlled, are connected to the nodes A and B and they can pull in current I from the nodes to which the respective current sources are connected. The two current sources of the respective pairs of the current sources are controlled by one of a pair of control signals and the inverse signal of the other signal. Then, the whole two pairs of the current sources which are switch-controlled can be set to the same type (N type). Two current sources are set to the same type (P type) and they are controlled by a common mode feedback loop.

公开(公告)号：JPH09284063A

公开(公告)日：1997-10-31

申请号：JP12961996

申请日：1996-05-24

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MERUKIOTSURE BURUTSUKOREERI ,  GAETAANO KOSENCHIINO ,  MARUKO DEMICHIERI ,  JIUSETSUPE PATSUTEI

IPC: G05F3/22 ,  G05F3/26 ,  H03F3/343 ,  H03K17/04 ,  H03K17/60

Abstract: PROBLEM TO BE SOLVED: To provide the current generator stage for integrated analog circuit in which a power-down time and a power-up time are considerably reduced. SOLUTION: A current generator stage 1 of a type having a current source 2 inserted between a 1st reference power supply voltage Vdd and, a 1st fixed reference voltage GND is provided with a at least one current mirror circuit 5 connecting to a current source 2 to produce at least one output current and a bias circuit 10 connecting to the current source 2 to apply a bias voltage to the current source. The bias circuit 10 of the current generator stage 1 has an energy storage circuit 11, and the energy storage circuit 11 is in the 1st circuit mode indicating a combination of a 1st reactance X1 and a 2nd reactance X2 when the current source 2 is set in the 1st operating mode and in the 2nd circuit mode to apply a prescribed bias voltage to the current source 2 when the current source 2 is in the 2nd operation mode.

公开(公告)号：JPH08288839A

公开(公告)日：1996-11-01

申请号：JP7824696

申请日：1996-03-06

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MERUKIOORE BURUTSUKORERI ,  JIYANFURANKO BUAI ,  SARUBATOORE PORUTARURI ,  MARUKO DEMICHIERI

IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

Abstract: PROBLEM TO BE SOLVED: To provide a fully integral phase locked loop(PLL) circuit which can optimize short-term stable characteristics while minimizing jitter by effectively removing the interference of high frequency noises or the like. SOLUTION: Concerning the fully integral PLL circuit having improved jitter characteristics, a 3rd pole p3 is led into the transfer function of PLL circuit by connecting a capacitor between the output of voltage/current conversion input step at a voltage controlled oscillator(VCO) 14 and the common ground node of circuit. The value of that capacitor is controlled while utilizing the same digital/analog converter(DAC) to be ordinarily used for controlling the time constant of low-pass loop filter 13. Through such a method, the gap between zero and the 3rd pole p3 in a frequency domain is kept constant, a damping factor is not changed but kept constant and ω0 of PLL circuit is fluctuated (increased).

公开(公告)号：JPH08335880A

公开(公告)日：1996-12-17

申请号：JP14376496

申请日：1996-05-14

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MERUKIOORE BURUTSUKORERI ,  MARUKO DEMICHIERI ,  JIYUSETSUPE PATSUTEI ,  BUARERIO PISATEI

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed processable secondary digital/analog converter(DACQ) which does not increase current consumption but rather decreases current consumption. SOLUTION: A DACQ composed of a pair of serially connected 1st and 2nd linear converter (DAC) has direct coupling between the output node of 1st DAC 1 and the R-2R type resistor circuit network of 2nd DAC 2, corresponding to the LSB step of R-2R type resistor circuit. A high impedance node, especially the input node of 2nd DAC is appropriately removed from a current path, so as to significantly reduce the problem of comparatively long settling time at the high impedance node (having a related originally large parasitic capacitance). The circuit is markedly simplified by the special architecture of this DACQ.

公开(公告)号：JPH07273636A

公开(公告)日：1995-10-20

申请号：JP32511194

申请日：1994-12-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MARUKO DEMICHIERI

IPC: H03K19/003 ,  H03K19/0185

Abstract: PURPOSE: To provide a TTL/CMOS interface circuit which has a tripping threshold value that is not affected by variation in temperature or a supply voltage. CONSTITUTION: An interface circuit includes an input stage Si and an output stage Su, and couples of inverters M2 and M3, and M5 and M6 in the input stage Si are applied with voltages through current mirror image circuits M1 and M4. A 1st inverter has an input terminal connected to a reference voltage VREF as high as a TTL tripping threshold value and an output terminal connected to the control terminal A of the current mirror image circuits M1 and M4. A 2nd inverter has an input terminal IN forming the input terminal of the interface circuit and an output terminal connected to the output stage Su. The interface circuit is supplied with a voltage equal to a CMOS type supply voltage.