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公开(公告)号：JP2540028B2
公开(公告)日：1996-10-02
申请号：JP32511294
申请日：1994-12-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
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公开(公告)号：JPH07326194A
公开(公告)日：1995-12-12
申请号：JP33746394
申请日：1994-12-28
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA
Abstract: PURPOSE: To obtain a voltage booster for a nonvolatile memory. CONSTITUTION: The voltage booster 1 comprises a charge pump 2 for generating a boost voltage Vboost on a boost line 3. The booster includes a voltage divider 5 to which a voltage V1 proportional to the boost voltage Vboost is applied, and also includes a comparator 6 to which a reference power 4 having a low reference voltage is applied, so that the charge pump 2 is put in its enable or disable state depending on a comparison result. A voltage limiter 8 is connected between the boost line 3 and ground. Further, a boost circuit 7 accelerates a voltage increase when the boost line is operated with low power, but a bus leading to the ground is made short to provide less power consumption.
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Patent Agency Ranking
公开(公告)号：JPH07249299A
公开(公告)日：1995-09-26
申请号：JP32511294
申请日：1994-12-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
Abstract: PURPOSE: To obtain an integrated programming circuit having redundancy by enabling the drive of a redundant programming load circuit according to the logical state of a data line through a switch circuit in response to a decoded output signal and inhibiting the drive of the other programming load circuit. CONSTITUTION: When a defective column address COLADD is supplied to a memory device, signals (OCO-OC3 and OCON-OC3N) are outputted from the identification code of a matrix part stored in a non-volatile register RR where this defective column address COLADD is stored. The output signals are supplied to a NAND gate 7 and in response to the output signal of the NAND gate 7, a switch circuit 6 enables the drive of a redundant programming load circuit PLOADR according to the logical state of a data line (DO-D15). At the same time, the gate 7 inhibits the drive of another programming load circuit (PLOADO-PLOAD15) through the switch circuit 6.
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公开(公告)号：DE69321245D1
公开(公告)日：1998-10-29
申请号：DE69321245
申请日：1993-12-29
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).
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公开(公告)号：DE69312305D1
公开(公告)日：1997-08-21
申请号：DE69312305
申请日：1993-12-28
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA
Abstract: A voltage booster (1) comprising a charge pump (2) for generating a boost voltage (Vboost) over a boost line (3). The booster comprises a comparator (6) which is supplied by a voltage divider (5) with a voltage V1 proportional to the boost voltage (Vboost), and by a reference source (4) with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump (2). A voltage limiter (8) is connected between the boost line (3) and ground; and a boost circuit (7) accelerates the voltage increase on the boost line following low-power operation in which the paths toward ground are interrupted for reducing consumption.
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公开(公告)号：DE69321245T2
公开(公告)日：1999-04-29
申请号：DE69321245
申请日：1993-12-29
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , MACCARRONE MARCO
Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).
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公开(公告)号：DE69312305T2
公开(公告)日：1998-01-15
申请号：DE69312305
申请日：1993-12-28
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA
Abstract: A voltage booster (1) comprising a charge pump (2) for generating a boost voltage (Vboost) over a boost line (3). The booster comprises a comparator (6) which is supplied by a voltage divider (5) with a voltage V1 proportional to the boost voltage (Vboost), and by a reference source (4) with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump (2). A voltage limiter (8) is connected between the boost line (3) and ground; and a boost circuit (7) accelerates the voltage increase on the boost line following low-power operation in which the paths toward ground are interrupted for reducing consumption.
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