VOLTAGE DOUBLER,VOLTAGE BOOSTER,AND VOLTAGE ADJUSTER

    公开(公告)号:JPH08275506A

    公开(公告)日:1996-10-18

    申请号:JP20714595

    申请日:1995-08-14

    Abstract: PROBLEM TO BE SOLVED: To obtain two ways of use for enabling finding out the advantageous use of a charge pump MOS voltage booster and boosters of this type. SOLUTION: A voltage booster is equipped with four MOS transistors (M1, M2, M3, M4) in place of a classical diode showing an undesirable voltage drop and with an oscillator having two output terminals and two corresponding charge transfer capacitors, in place of a classical oscillator of a single output having relevant charge transfer capacitors. In this method, the undesirable voltage drop substantially does not exist, and ripples are reduced without making a circuit complicated.

    8.
    发明专利
    未知

    公开(公告)号:DE69533308T2

    公开(公告)日:2004-11-25

    申请号:DE69533308

    申请日:1995-05-16

    Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (VIN1) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (VIN2) present on a terminal (S11) of the auxiliary transistor (M11). The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.

    9.
    发明专利
    未知

    公开(公告)号:DE69421075T2

    公开(公告)日:2000-03-02

    申请号:DE69421075

    申请日:1994-06-10

    Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).

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