公开(公告)号：EP0321860A2

公开(公告)日：1989-06-28

申请号：EP88120975.3

申请日：1988-12-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Re, Danilo

IPC: H01L21/82 ,  H01L21/316 ,  H01L27/06 ,  H01L29/92

CPC classification number: H01L28/40 ,  H01L21/8238 ,  H01L27/0688 ,  H01L27/092

Abstract: A process for manufacturing integrated capacitors in CMOS technology, comprising the steps of: producing, in a substrate (1) of semiconductor material having a first type of conductivity, at least one well (4) with the opposite type of conductivity, defining the active areas, producing insulation regions (3, 3′), depositing a first conducting layer (6) of polycrystalline silicon adapted to form the gate regions and the lower plates of the capacitors, depositing a layer (7) of silicon oxide at low temperature, to form the dielectric of the capacitors, depositing a second layer (8) of polycrystalline silicon to form the second plate of the capacitors, shaping the polycrystalline silicon and silicon oxide layers, implanting and diffusing the source (9) and drain (10) regions of the CMOS transistors, providing the insulation layer (11), the metallic connecting layer (12), and final covering with a layer of protective insulation.

Abstract translation: 一种用于制造CMOS技术的集成电容器的方法，包括以下步骤：在具有第一类型导电性的半导体材料的衬底（1）中制造具有相反类型导电性的至少一个阱（4），限定有源 产生绝缘区域（3,3分钟），沉积适于形成电容器的栅极区域和下部板的多晶硅的第一导电层（6），在低温下沉积氧化硅层（7） 以形成电容器的电介质，沉积多晶硅的第二层（8）以形成电容器的第二板，对多晶硅和氧化硅层进行成形，将源极（9）和漏极（10）区域 的CMOS晶体管，提供绝缘层（11），金属连接层（12）以及具有保护绝缘层的最终覆盖层。

公开(公告)号：EP0435534B1

公开(公告)日：1995-11-08

申请号：EP90313667.9

申请日：1990-12-14

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Re, Danilo ,  Maurelli, Alfonso

IPC: H01L21/82

CPC classification number: H01L27/11526 ,  H01L21/8221 ,  H01L21/823842 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S148/014

公开(公告)号：EP0575688B1

公开(公告)日：1998-05-27

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/11266 ,  H01L27/112

公开(公告)号：EP0575688A2

公开(公告)日：1993-12-29

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与单元的沟道区域去耦合而被有利地编程在相对较先进的制造阶段，以通过将量子点 足以反转与沟道区相邻的漏极区的一部分中的导电性的类型。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的有意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至更晚阶段进行。

公开(公告)号：EP0321860A3

公开(公告)日：1990-03-07

申请号：EP88120975.3

申请日：1988-12-15

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Re, Danilo

IPC: H01L21/82 ,  H01L21/316 ,  H01L27/06 ,  H01L29/92

CPC classification number: H01L28/40 ,  H01L21/8238 ,  H01L27/0688 ,  H01L27/092

Abstract: A process for manufacturing integrated capacitors in CMOS technology, comprising the steps of: producing, in a substrate (1) of semiconductor material having a first type of conductivity, at least one well (4) with the opposite type of conductivity, defining the active areas, producing insulation regions (3, 3′), depositing a first conducting layer (6) of polycrystalline silicon adapted to form the gate regions and the lower plates of the capacitors, depositing a layer (7) of silicon oxide at low temperature, to form the dielectric of the capacitors, depositing a second layer (8) of polycrystalline silicon to form the second plate of the capacitors, shaping the polycrystalline silicon and silicon oxide layers, implanting and diffusing the source (9) and drain (10) regions of the CMOS transistors, providing the insulation layer (11), the metallic connecting layer (12), and final covering with a layer of protective insulation.

公开(公告)号：EP0575688A3

公开(公告)日：1994-03-16

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 采用MOS或CMOS技术制造的具有LDD单元的ROM存储器可以有利地在相对高级的制造阶段通过将已形成的漏极区与单元的沟道区解耦以通过注入一定量的掺杂剂而永久地形成非导电（编程） 足以反转与沟道区相邻的漏极区的一部分中的导电类型。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电类型的晶体管的源极/漏极区的有意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至更晚的阶段进行。

公开(公告)号：EP0435534A2

公开(公告)日：1991-07-03

申请号：EP90313667.9

申请日：1990-12-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Re, Danilo ,  Maurelli, Alfonso

IPC: H01L21/82

CPC classification number: H01L27/11526 ,  H01L21/8221 ,  H01L21/823842 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S148/014

Abstract: An integrated circuit is manufactured by forming first and second regions on silicon dioxide (4, 6) on a semiconductor substrate (1). The first and second regions comprise a polycrystalline silicon layer (7), an insulating layer (8), and a polycrystalline silicon layer (9). The layers (8) and (9) are removed from the second regions and a second insulating layer (10) formed on the second regions. A third polycrystalline layer (11) is formed on the first and second regions. The first regions may be formed as EPROM memory cells and the second regions as capacitors.

Abstract translation: 通过在半导体衬底（1）上的二氧化硅（4,6）上形成第一和第二区域来制造集成电路。 第一和第二区域包括多晶硅层（7），绝缘层（8）和多晶硅层（9）。 从第二区域去除层（8）和（9），形成在第二区域上的第二绝缘层（10）。 在第一和第二区域上形成第三多晶层（11）。 第一区域可以形成为EPROM存储单元，第二区域形成为电容器。