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    Method for recovering floating-gate memory cells with low threshold voltage in flash-EEPROM memory devices
    4.
    发明公开
    Method for recovering floating-gate memory cells with low threshold voltage in flash-EEPROM memory devices 失效
    一种用于与在快闪EEPROM存储器装置的低阈值电压恢复浮置栅极存储单元的方法。

    公开(公告)号：EP0621604A1

    公开(公告)日：1994-10-26

    申请号：EP93830173.6

    申请日：1993-04-23

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Bez, Roberto ,  Fratin, Lorenzo ,  Maurelli, Alfonso ,  Cantarelli, Daniele ,  Ghezzi, Paolo

    IPC: G11C16/06

    CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404

    Abstract: A method for recovering flash-EEPROM memory cells (MC) with low threshold voltage is described. The method provide for the simultaneous application of a first voltage with a first prescribed value (V D ) and of a second voltage with a second prescribed value (V G ) to drain regions (D) of each of said memory cells (MC) and to gate regions (G) of the memory cell (MC) for a prescribed time interval suitable for submitting said memory cells (MC) to a prescribed threshold voltage shift. A reference ground voltage (GND) is concurrently applied to source regions (S) of said memory cells (MC).

    Abstract translation: 描述了一种用于回收快闪EEPROM的存储单元用低阈值电压的方法（MC）。 该方法提供与第一规定值（VD）的第一电压的同时施加，并与一个第二规定值（VG）的第二电压的每一个所述存储单元的区域（D）（MC）和漏极到栅极 适合于提交所述存储单元（MC），以规定的阈值电压偏移规定的时间间隔存储单元（MC）的区域（G）。 参考地电压（GND）被并行地施加到所述存储器单元的源极区域（S）（MC）。

    Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with EEPROM memory cells
    6.
    发明公开
    Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with EEPROM memory cells 失效
    一种制备组件，其用于限制所述编程电压和用于电压的与EEPROM存储单元的电组件中的稳定化工艺。

    公开(公告)号：EP0426241A2

    公开(公告)日：1991-05-08

    申请号：EP90202840.6

    申请日：1990-10-24

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Cappelletti, Paolo ,  Corda, Giuseppe ,  Ghezzi, Paolo ,  Riva, Carlo ,  Vajana, Bruno

    IPC: H01L21/82 ,  H01L21/329 ,  H01L27/02 ,  G11C16/04

    CPC classification number: H01L29/66106 ,  H01L27/115 ,  H01L27/11517 ,  Y10S148/174 ,  Y10S438/983

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    Abstract translation: 制造过程包括形成N型水槽（2）中的在单结晶硅的第一步骤的底物（1）中，形成有源区（14）中的所述排水池的表面上的第二步骤（2） N-掺杂剂的植入在表面区域的第三步骤（4）所述有源区域内的水槽（2）（14），栅氧化物层（5）的生长在具有N-所述区域的第四步骤的 掺杂剂，的N +注入的第五步骤（6; 9）在所述N-型区，P +注入（7; 12）的第六步骤在后期反弹位移位置相对于所述N +区域和形成外部触点中的第七步 （8，18; 13，23，33），用于所述N +和P +区域。 因此，存在所获得的齐纳二极管限幅器，具有一个截止电压的所有其是随时间稳定的，没有太大的依赖于温度，并且不要求另外的工艺步骤相对于那些通常有必要对EEPROM的存储单元的特征。

    Process for the manufacture of a Zener Diode for EEPROM devices
    10.
    发明公开
    Process for the manufacture of a Zener Diode for EEPROM devices 失效
    Herstellungsverfahren einer齐纳二极管f EEPROM EEPROM。

    公开(公告)号：EP0643418A1

    公开(公告)日：1995-03-15

    申请号：EP93830365.8

    申请日：1993-09-10

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Ghezzi, Paolo ,  Maurelli, Alfonso

    IPC: H01L21/329 ,  H01L29/866 ,  H01L27/06

    CPC classification number: H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

    Abstract: A process for the manufacture of a zener-diode as an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well (2) on a single-crystal silicon substrate (1); a step of formation of an active area (4) on the surface of said N type well (2); a step of growth of a thin gate oxide layer (5) over said active area (4); a step of implantation of a first heavy dose of N type dopant into said N type well (2) to obtain an N type region (6; 18; 19); a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region (6; 18) to obtain an N+ contact region (7; 20) to both the N type well (2) and said N type region (6; 18; 19); a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region (6; 19) to form a P+ region (8; 21).
    The N+ region (7; 20) is of annular shape. The zener-diode can also be gated. All manufacturing steps for the zener-diode correspond to manufacturing steps of the flash EEPROM memory device.

    Abstract translation: 在闪存EEPROM存储器件中制造齐纳二极管作为集成限压器和稳定器部件的工艺包括在单晶硅衬底（1）上形成N型轻掺杂阱（2）的步骤; 在所述N型井（2）的表面上形成活性区域（4）的步骤; 在所述有源区（4）上生长薄栅氧化层（5）的步骤; 将第一重剂量的N型掺杂剂注入所述N型阱（2）以获得N型区域（6; 18; 19）的步骤; 将高于所述第一重剂量的第二重剂量的N型掺杂剂的第二重剂量注入所述N型区域（6; 18）以获得N型阱（2; N）的N +接触区域（7; 20）的步骤 ）和所述N型区域（6; 18; 19）; 将高于所述第一重剂量的第三重剂量的P型掺杂剂注入到所述N型区域（6; 19）中以形成P +区域（8; 21）的步骤。 N +区域（7; 20）是环形的。 齐纳二极管也可以选通。 齐纳二极管的所有制造步骤对应于快闪EEPROM存储器件的制造步骤。

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