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    EEPROM memory cells matrix with double polisilicon level and relating manufacturing process
    2.
    发明公开
    EEPROM memory cells matrix with double polisilicon level and relating manufacturing process 失效
    EEPROM-Speicherzellenmatrix mit Doppelter Polysiliziumebene und Herstellungsverfahren

    公开(公告)号：EP0730277A1

    公开(公告)日：1996-09-04

    申请号：EP95830064.2

    申请日：1995-02-28

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Pio, Federico ,  Paruzzi, Paola

    IPC: G11C16/00 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    Abstract: A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor (2) of the floating gate type which includes two layers of polysilicon (5 and 8) superposed on each other and separated by an intervening layer (7) of a dielectric material, and a selection transistor (3) having a gate (13) which comprises a first layer of polysilicon (5). The gates (13) of the selection transistors (3) in one row of said matrix are connected electrically together by a selection line (c2) comprising a second layer of polysilicon (8) overlying the first layer (5). The intermediate layer of dielectric material (7) is also partly interposed between the first and second layers of polysilicon (5 and 8) such that the two layers (5 and 8) are in contact at at least one zone (21) of said selection line (c2). Preferably, the contact zone (21) is formed over field oxide regions (20) and is away from the edges of the selection line (c2)
    The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

    Abstract translation: 具有MOS技术的双重多晶硅级并且被布置成行和列的EEPROM存储单元的矩阵被单片地集成在半导体材料的衬底上。 每个单元串联包括浮置型晶体管（2），该晶体管包括彼此叠置并由电介质材料的中间层（7）分开的两层多晶硅（5和8），以及选择晶体管 （3）具有包括第一多晶硅层（5）的栅极（13）。 所述矩阵的一行中的选择晶体管（3）的栅极（13）通过包括第一层（5）上的第二多晶硅层（8）的选择线（c2）电连接在一起。 电介质材料（7）的中间层也部分插入在第一和第二层多晶硅（5和8）之间，使得两个层（5和8）在所述选择的至少一个区域（21）处接触 线（c2）。 优选地，接触区域（21）形成在场氧化物区域（20）上并且远离选择线（c2）的边缘。矩阵可以有利地通过自对准类型的过程来制造，而不需要进行处理 更复杂

    Circuit structure for a memory matrix and corresponding manufacturing method
    3.
    发明公开
    Circuit structure for a memory matrix and corresponding manufacturing method 失效
    SchaltungsstrukturfürSpeichermatrix und entsprechende Herstellungsverfahren。

    公开(公告)号：EP0637035A1

    公开(公告)日：1995-02-01

    申请号：EP93830339.3

    申请日：1993-07-29

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Pio, Federico ,  Riva, Carlo ,  Lucherini, Silvia c/o SGS-Thomson

    IPC: G11C16/04 ,  H01L27/115

    CPC classification number: H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

    Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).

    Abstract translation: 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行（3）和列（4）的单元（2）的矩阵，每行（3）设置有字线（WL ）和控制栅极线（CG）以及具有位线（BL）的每列（4）。 此外，位线（BL）被收集成同时可寻址的相邻线的组或字节（9）。 矩阵中的每个单元（2）包括一个浮动栅晶体管（12），该浮栅晶体管（12）耦合到与控制栅极线（CG）连接的控制栅极（8），并串联连接到选择晶体管（5）。 每个单独字节（9）的单元（2）也共享它们各自的源区域（6），这些区域对于每个字节（9）在结构上是独立的，并且被引导到沿矩阵延伸的对应的源寻址行（SL） 列（7）。

    Method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device, and integrated structure for actuating such method
    10.
    发明公开
    Method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device, and integrated structure for actuating such method 失效
    用于驱动该方法提供由负的编程电压和集成结构的非易失性存储器装置的方法。

    公开(公告)号：EP0654791A1

    公开(公告)日：1995-05-24

    申请号：EP93830464.9

    申请日：1993-11-24

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Baldi, Livio ,  Pio, Federico

    IPC: G11C16/06

    CPC classification number: G11C16/30 ,  G11C16/12

    Abstract: A method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device provides for charging a capacitor (C;C1-Cn) to a positive high voltage by connecting, through first switching means (TX,TY;TE1-TEn,TF1-TFn), a first plate (A;A1-An) of the capacitor (C;C1-Cn) to a positive high-voltage supply (Vpp) and connecting, through second switching means (TB;TZ;TD1-TDn), a second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn), which is also operatively connected to the control gate of at least one memory cell, to a reference voltage supply (GND), and for successively connecting, through said first switching means (TX,TY;TE1-TEn,TF1-TFn) the first plate (A;A1-An) of the capacitor (C;C1-Cn) to the reference voltage supply (GND) and disconnecting the second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn) from the reference voltage supply (GND) to obtain a negative voltage on said second plate (B;B';B1-Bn) voltage.

    Abstract translation: 一种用于在非易失性存储器装置提供负的编程电压到非易失性存储器单元的方法提供了一个电容器充电;通过连接，通过第一开关装置（TX，TY（C C1-Cn）的对正的高电压; TE1 日，TF1 TFN），一第一板（A;所述电容器的A1-An）的（C; C1-Cn）的一个正的高电压电源（VPP）和连接，通过第二开关装置（TB; TZ; TD1-TDN），第二板（B;电容器（C的B1-BN）; B” C1-Cn）的，所有这些是由此可操作地连接到至少一个存储单元的控制栅极，一个参考电压源 （GND），并且用于连续地连接，通过所述第一开关装置（TX，TY; TE1-TEN，TF1 TFN）的第一板;所述电容器的（A A1-An）的（C; C1-Cn）的所述参考 电源电压（GND）和断开所述第二板中的电容器的（B; B1-BN; B”）;从所述基准电压源（GND）（C C1-CN），以获得在所述第二板（B负电压; 电压B1-BN）; B”。

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