公开(公告)号：WO2008091221A3

公开(公告)日：2008-09-18

申请号：PCT/SE2008050093

申请日：2008-01-25

Applicant: SILEX MICROSYSTEMS AB ,  EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C3/00 ,  H01L23/043

CPC classification number: H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The invention relates in one aspect to a method of micro-packaging a component. At least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of said substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. The invention also relates to a micro-packaged electronic or micromechanic device, comprising a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing. An electronic or micromechanic component is attached to said electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.

Abstract translation: 本发明在一个方面涉及一种微封装部件的方法。 提供至少第一和第二半导体衬底，其中一个具有电连接（通孔）。 在任一个所述衬底中或在两者中的凹陷被蚀刻。 元件设置在通孔上方并与其连接。 基材被接合以形成密封包装。 本发明还涉及一种微封装电子或微机械装置，其包括具有穿过壳体底部的电连接的半导体材料的薄壁壳体。 电子或微机械部件连接到所述电连接连接，并且封装被气密密封以保持期望的气氛，在盒内适当的真空。

公开(公告)号：EP2005467A4

公开(公告)日：2011-05-18

申请号：EP07709446

申请日：2007-01-31

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

公开(公告)号：SE0850083L

公开(公告)日：2010-05-20

申请号：SE0850083

申请日：2008-11-19

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

公开(公告)号：SE537214C2

公开(公告)日：2015-03-03

申请号：SE1150413

申请日：2008-11-19

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJÖRN ,  KÄLVESTEN EDVARD ,  BAUER TOMAS

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498

公开(公告)号：EP2121511A4

公开(公告)日：2014-07-02

申请号：EP08705365

申请日：2008-01-25

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJÖRN ,  KÄLVESTEN EDVARD ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C3/00 ,  H01L23/055 ,  H01L23/14

CPC classification number: H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

Abstract translation: 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。 还描述了用于制造包括晶片中的蚀刻沟槽以及用绝缘材料填充沟槽的这种衬底的方法。

公开(公告)号：EP2106617A4

公开(公告)日：2015-04-15

申请号：EP08705364

申请日：2008-01-25

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJÖRN ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/055 ,  H01L23/14 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

公开(公告)号：SE534510C2

公开(公告)日：2011-09-13

申请号：SE0850083

申请日：2008-11-19

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/50 ,  H01L23/48

公开(公告)号：SE0850083A1

公开(公告)日：2010-05-20

申请号：SE0850083

申请日：2008-11-19

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

IPC: B81C1/00 ,  B81B7/00 ,  H01L21/50 ,  H01L23/48

公开(公告)号：SE0801620L

公开(公告)日：2008-10-30

申请号：SE0801620

申请日：2007-01-31

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

公开(公告)号：SE533579C2

公开(公告)日：2010-10-26

申请号：SE0700172

申请日：2007-01-25

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C3/00 ,  H01L23/04 ,  H01L23/06 ,  H01L25/10