公开(公告)号：WO2008091221A3

公开(公告)日：2008-09-18

申请号：PCT/SE2008050093

申请日：2008-01-25

Applicant: SILEX MICROSYSTEMS AB ,  EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

IPC: B81B7/00 ,  B81C3/00 ,  H01L23/043

CPC classification number: H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The invention relates in one aspect to a method of micro-packaging a component. At least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of said substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. The invention also relates to a micro-packaged electronic or micromechanic device, comprising a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing. An electronic or micromechanic component is attached to said electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.

Abstract translation: 本发明在一个方面涉及一种微封装部件的方法。 提供至少第一和第二半导体衬底，其中一个具有电连接（通孔）。 在任一个所述衬底中或在两者中的凹陷被蚀刻。 元件设置在通孔上方并与其连接。 基材被接合以形成密封包装。 本发明还涉及一种微封装电子或微机械装置，其包括具有穿过壳体底部的电连接的半导体材料的薄壁壳体。 电子或微机械部件连接到所述电连接连接，并且封装被气密密封以保持期望的气氛，在盒内适当的真空。

公开(公告)号：WO2007070004A3

公开(公告)日：2007-08-23

申请号：PCT/SE2006050582

申请日：2006-12-14

Applicant: SILEX MICROSYSTEMS AB ,  KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  CORMAN THIERRY

Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  CORMAN THIERRY

IPC: A61B5/042 ,  A61B5/151 ,  A61B5/153 ,  A61M5/158 ,  A61M25/06 ,  A61M37/00 ,  A61N1/18 ,  G01N33/483 ,  G01R1/073

CPC classification number: A61M37/0015 ,  A61B5/053 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0046 ,  A61M2037/0053 ,  A61N1/0502 ,  A61N1/0551 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

Abstract translation: 本发明在总体方面涉及一种在衬底上制造垂直突出元件的方法，所述元件具有包括至少一个倾斜表面的尖端和在所述衬底和所述尖端之间延伸的细长主体部分。 该方法包括形成所述倾斜表面的各向异性，依赖于晶面的蚀刻; 以及形成所述细长主体部分的各向异性非晶体平面依赖蚀刻; 结合限定所述突出元件以具有预定基部几何形状的适当图案化工艺。

公开(公告)号：EP2005467A4

公开(公告)日：2011-05-18

申请号：EP07709446

申请日：2007-01-31

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

公开(公告)号：EP1962679A4

公开(公告)日：2011-04-13

申请号：EP06824640

申请日：2006-12-14

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  CORMAN THIERRY

IPC: A61B5/042 ,  A61B5/151 ,  A61B5/153 ,  A61M5/158 ,  A61M25/06 ,  A61M37/00 ,  A61N1/18 ,  G01N33/483

CPC classification number: A61M37/0015 ,  A61B5/053 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150984 ,  A61M2037/003 ,  A61M2037/0046 ,  A61M2037/0053 ,  A61N1/0502 ,  A61N1/0551 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

公开(公告)号：EP2377154A4

公开(公告)日：2012-06-27

申请号：EP09835356

申请日：2009-12-23

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  AAGREN PETER ,  SVEDIN NIKLAS

IPC: G02B26/08 ,  B81B7/00 ,  B81C1/00 ,  H01L21/768

CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

公开(公告)号：SE1151268A1

公开(公告)日：2013-06-23

申请号：SE1151268

申请日：2011-12-22

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  ERIKSSON ANDERS

IPC: H01L21/762 ,  A61M37/00 ,  B81C1/00 ,  H01L21/768

公开(公告)号：SE536058C2

公开(公告)日：2013-04-16

申请号：SE1150429

申请日：2011-05-12

Applicant: SILEX MICROSYSTEMS AB

Inventor： KAELVESTEN EDVARD

IPC: B01L3/00 ,  C03B23/24 ,  G01N21/05 ,  G01N35/08

公开(公告)号：SE1051391A1

公开(公告)日：2010-12-30

申请号：SE1051391

申请日：2008-12-23

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  SVEDIN NIKLAS

IPC: G02B26/08 ,  B81B7/00 ,  H01L23/522

公开(公告)号：SE0802663A1

公开(公告)日：2010-06-24

申请号：SE0802663

申请日：2008-12-23

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  SVEDIN NIKLAS ,  AAGREN PETER

IPC: H01L23/522 ,  B81B7/00 ,  B81C1/00 ,  G02B26/08 ,  H01L21/768

公开(公告)号：SE0850083L

公开(公告)日：2010-05-20

申请号：SE0850083

申请日：2008-11-19

Applicant: SILEX MICROSYSTEMS AB

Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.