公开(公告)号：DE10213556A1

公开(公告)日：2002-10-17

申请号：DE10213556

申请日：2002-03-26

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI ,  KOBAYASHI TOSHIO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device comprises a gap (35) formed between wirings (32A, 32B, 32C) on a substrate. The gap is filled with gas having a thermal conductivity equal to or higher than three times of air at 0 deg C. An Independent claim is included for a wiring forming method in a semiconductor device which comprises: (i) forming a wiring and filling layer filled with wirings on a substrate; (ii) forming a gas permeable film on the wiring and filling layer; (iii) removing the filling layer through the gas permeable film to form a gap between the wirings; (iv) filling a gas having a thermal conductivity equal or higher than three times that of air at 0 deg C through the gas permeable film into gap; and (v) forming a gas impermeable film on the gas permeable film.

公开(公告)号：JPH08153690A

公开(公告)日：1996-06-11

申请号：JP31905194

申请日：1994-11-29

Applicant: SONY CORP

Inventor： YAMANAKA HIDEO ,  HAYAFUJI TAKANORI ,  AOYAMA JUNICHI

IPC: H01L21/288 ,  C23C18/31 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40

Abstract: PURPOSE: To provide a practicable semiconductor device using electroless plating technique and its manufacturing method,and a wiring formation method by solving a problem of contamination which was a difficult point when electroless plating technique is applied to a field of a semiconductor device. CONSTITUTION: A connection structure for burying a conductive matter 4 in a connection hole 3 formed in an insulation layer 2 on a semiconductor substrate 1 such as Si is provided, a connection hole has a barrier layer 5 all over a bottom surface and a side surface and the buried conductive matter 4 is a metal material formed by electroless plating. A connection hole 3 is shaped in the insulation layer 2, the barrier layer 5 is formed all over a bottom surface and a side surface of a connection hole and a conductive matter is buried in a connection hole by electroless plating. After a taper hole is formed on a lower wiring when the occasion demands, a connection hole is formed in conformity to a lower wiring, and a groove for upper wiring formation is constituted so that at least a part thereof overlaps with the connection hole in the same layer insulation film and it is filled up with electroless plating for forming a wiring.

公开(公告)号：JPS6468949A

公开(公告)日：1989-03-15

申请号：JP22618987

申请日：1987-09-09

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI

IPC: H01L29/78 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/52

Abstract: PURPOSE:To the manufacturing process of a semiconductor device easy, by commonly using a semiconductor layer and an insulating film for different functions. CONSTITUTION:A polycrystalline Si layer 13a and an Si3N4 film 14 are formed on an SiO2 film 12 on a P-type Si substrate 11. The specified thicknesses of the film 14 and the layer 13a in an element isolating region are removed. With the film 14 as a mask, an SiO2 film 15 is formed by thermal oxidation. A hole 16 penetrating the layer 13a and the film 12 is formed. An exposed part 17 is formed on the surface of the substrate 11. A polycrystalline Si layer 13b is formed. P is diffused into the Si layers 13b and 13a. A silicide layer 22 is formed, and wiring layers 23 are formed together with the Si layer 13b. The bird's beak of the insulating film 15 is made small with the semiconductor layer 13a. The layer 13a prevents the etching of the insulating film 12 when the exposed part 17 is provided. The insulating film 12 alleviates stress between the substrate 11 and the oxidation resisting film 14 when the insulating film 15 is formed. The film 12 insulates the substrate 11 and the wiring layers 23. Therefore, the manufacturing process of the semiconductor device is made easy.

公开(公告)号：JPS63128731A

公开(公告)日：1988-06-01

申请号：JP27622386

申请日：1986-11-19

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI

IPC: H01L21/3205

Abstract: PURPOSE:To enable even shallow and fine openings to be easily formed, by filling the openings formed in the areas of an insulating film corresponding to electrically connected areas and concurrently forming a conductive layer and etching the conductive layer until a top part of the insulating film is exposed and performing wiring on the conductive layer whose surface is flattened. CONSTITUTION:A gate insulating film 12, an element-isolation region 13, gate electrodes 14a to 14c, and source.drain regions 15a to 15c are in the vicinity of a surface of a semiconductor substrate 11. When a layer-insulation film 17 is piled on them, contact holes 21a and 21b are formed in parts corresponding to contact parts in the source.drain regions 15a and 15b. While these contact holes are buried, a surface of a conductive layer 22 formed to cover the layer- insulation film 17 is flattened, and a resist and the conductive layer 22 are etched until a top part of the layer-insulation film 17 is exposed, so that an approximately flat surface can be formed of the conductive layer 22 and the layer-insulation film 17. When a first layered interconnection 23 is made to come in contact with the gate electrode 14a and the source.drain region 15a, a contact hole 25 is formed in only a layer-insulation film 24, and the interconnection 23 is made to come in contact with only a conductive layer 22a.

公开(公告)号：JP2000183161A

公开(公告)日：2000-06-30

申请号：JP35277598

申请日：1998-12-11

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L27/00

Abstract: PROBLEM TO BE SOLVED: To reduce the time required for manufacturing electronic device having a multilayer wiring and to improve the manufacturing yield. SOLUTION: A CMOS transistor is formed on an Si substrate 2, and an interlayer insulation film 22, having wiring grooves 23, 24 in the upper part thereof via a BPSG film 17 for manufacturing a first substrate 1, while after a three-layer wiring is formed on a glass substrate 31, wirings 54, 55 having pattern shapes with mirror image relation with the pattern shapes of the grooves 23, 24 are formed to manufacture a second substrate 30. After the first substrate 1 and the second substrate 30 are interposed in such a way that they face each other to embed the wiring 54, 55 in the grooves 23, 24, the first and second substrates are heated, and then they are bonded. A glass substrate 31 is removed from the second substrate by etching a film 32 for removal, so that a CMOSLSI is manufactured.

公开(公告)号：JPH11251294A

公开(公告)日：1999-09-17

申请号：JP4745998

申请日：1998-02-27

Applicant: SONY CORP

Inventor： KADOMURA SHINGO ,  AOYAMA JUNICHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213

Abstract: PROBLEM TO BE SOLVED: To enable the formation of low resistance contacts by avoiding oxidizing a metal silicide layer, due to a resist ashing after a step of boring connection holes facing the metal silicide layer formed as a thin film in a highly integrated circuit device. SOLUTION: Nitrogen type active species is used for a step of removing a resist mask 10. The resist becomes a reaction product of CH or CN and is removed. On a metal silicide layer 8, no oxide layer is formed due to the nitrogen type active species. Consequently, the soft etching after the resist ashing is not required or only slightly, thereby avoiding damaging the metal silicide layer 8 which is formed as a thin film.

公开(公告)号：JPH1154612A

公开(公告)日：1999-02-26

申请号：JP20481997

申请日：1997-07-30

Applicant: SONY CORP

Inventor： KOYAMA KAZUHIDE ,  AOYAMA JUNICHI

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress the decrease of a contact area between a groove wiring and a conduction material embedded into a connection hole, can reduce contact resistance and can secure the reliability of the groove wiring, even if connection hole and the wiring groove are dislocated and formed for combination deviation in a lithographic process, and to provide a manufacture method. SOLUTION: A lower layer wiring groove 3 is formed in an interlayered insulating film 2 and a lower-layer groove wiring 5, where a TiN/Ti film 4 is set to be a base film is formed. Then, an antireflection film 6, an interlayered insulating film 7, an etching stopper layer 8, an interlayered insulating film 9 are sequentially formed, and a connection hole 10 is formed. Then, Al is embedded into the connection hole 10 by a height lower than the base of the upper-layer wiring groove 12. The upper-layer wiring groove 12 is formed on the interlayered insulating film 9, a TiN/Ti film 13 and an Al alloy film are formed on the entire face, and the Al alloy film is reflowed with high pressure. Al alloy is embedded into the upper part of the connection hole 10 and the upper-layer wiring groove 12. The Al alloy film in a part, excepting the inner part of the upper layer wiring groove and the TiN/Ti film 13, is removed by a CMP method, and the upper layer groove wiring 16 is formed.

公开(公告)号：JP2002289687A

公开(公告)日：2002-10-04

申请号：JP2001090292

申请日：2001-03-27

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI ,  KOBAYASHI TOSHIO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which problems such as heat diffusion inferiority in wiring technology in a hollow space are dissolved. SOLUTION: The semiconductor device has a cavity 15 formed between wirings 12 formed on a substrate 10. The cavity 15 is filled with gas 16 having heat conductivity at least three times than that of air at 0 deg.C.

公开(公告)号：JP2002252281A

公开(公告)日：2002-09-06

申请号：JP2001052197

申请日：2001-02-27

Applicant: SONY CORP

Inventor： AOYAMA JUNICHI

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To improve the yield of wiring process and the reliability of a semiconductor device. SOLUTION: When the Al wiring of an upper layer is connected with the Al wiring 3 of an under layer buried in a trench 2a formed in an interlayer insulation film 2 through a connecting column 5, a growth suppression film 4 having an opening 4a the width of which is wider than that of an Al wiring 3 is formed on an interlayer insulation film and on the Al wiring 3. Then, the connecting column 5 is formed in this condition on the Al wiring 3 in the opening 4a self aligned to the Al wiring 3 by growing Al or the like by selective CVD method or the like.

公开(公告)号：JPH1167763A

公开(公告)日：1999-03-09

申请号：JP22505897

申请日：1997-08-21

Applicant: SONY CORP

Inventor： MAEDA KEIICHI ,  AOYAMA JUNICHI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured at high manufacturing yield with a pad of wiring or part of wiring requiring a larger width which is not affected by dishing by a chemical mechanical polishing, when the wiring is formed by using a buried wiring technique, and a manufacturing method therefor. SOLUTION: A pad 1 of a lower layer wiring and a pad 2 of an upper layer wiring are provided in a square pad region of 100 μm square. The pads 1, 2 are constituted of groove wirings 3, 4, which are narrower than the entire sizes of the pads 1, 2. The width of the groove wirings 3, 4 is set at 0.4 μm. The groove wirings 3, 4 are made as a picture drawn in a single stroke, such that they form the shape of the pads 1, 2 as a whole in the pad regions.