公开(公告)号：JP2003115594A

公开(公告)日：2003-04-18

申请号：JP2001310560

申请日：2001-10-05

Applicant: SONY CORP ,  ST LCD KK

Inventor： TANAKA TSUTOMU ,  MANO MICHIO ,  TORIYAMA SHIGETAKA ,  FUJINO MASAHIRO ,  KOMATSU HIROSHI ,  TAKEDA HIROHISA

IPC: G02F1/1368 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve the yield of a product by preventing defects in gate breakdown strength in a bottom gate type TFT. SOLUTION: The manufacturing method of a bottom gate type TFT 100A includes a step (1) of forming a gate electrode on a substrate, a step (2) of forming a gate insulating film on the gate electrode 2, a step (3) of forming a laminate made up of an protective insulating film 8 having a film thickness of 100 nm or smaller while an active-layer antecedent film (polysilicon film 7) and the protective insulating film 8 are laminated on the gate insulating film, a step (4) of implanting a dopant in an LDD region or in a source/drain region of the active-layer precursor film 8 through the protective insulating film 8, a step (5) of activating the implanted dopant and causing the other non-dopant part to be an active layer, a step (6) of modifying the quality of all or part of the protective insulating film 8, a step (7) of forming an interlayer insulating film on the modified protective insulating film 8, and a step (8) of forming a source/drain electrode on the interlayer insulating film.

公开(公告)号：JP2009037115A

公开(公告)日：2009-02-19

申请号：JP2007202867

申请日：2007-08-03

Applicant: Sony Corp ,  Sony Mobile Display Corp ,  ソニーモバイルディスプレイ株式会社 ,  ソニー株式会社

Inventor： TANAKA TSUTOMU ,  YAMADA YASUHIRO ,  TAKEDA HIROHISA

IPC: G09F9/30 ,  H01L21/768 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a contact structure interconnecting wires of three or more layers most efficiently and in the minimum area in the interconnection, and also to provide its manufacturing method, and a display device. SOLUTION: N (three or more) conductive layers 202-204 are laminated and formed on a substrate 201, n conductive layers are interconnected via a contact pattern, one main contact area in which a contact pattern is formed has (n-1) connecting areas 211 and 212 for interconnecting (n-1) conductive layers 202 and 203, the conductive layer upper than the first layer in the laminated direction (normal direction to the main surface of the substrate 201) to the substrate 201, of (n-1) conductive layers, is formed so that the terminal end faces part of the edge of a contact pattern CPTN, and (n-1) conductive layers are electrically interconnected through the n-th conductive layer. The n-th conductive layer is formed so that a contact hole as the contact pattern CPTN is filled up. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有接触结构的半导体器件，该接触结构将互连中最有效且最小的区域中的三层或更多层的布线互连，并提供其制造方法和显示装置。 解决方案：在衬底201上层叠并形成N（三个或更多个）导电层202-204，n个导电层经由接触图案互连，其中形成接触图案的一个主接触区域具有（n- 1）用于互连（n-1）导电层202和203的连接区域211和212，在衬底201上的层叠方向（与衬底201的主表面的法线方向）比第一层高的导电层， （n-1）个导电层，使得终端面向接触图案CPTN的边缘的一部分，并且（n-1）个导电层通过第n导电层电互连。 形成第n导电层，使得作为接触图案CPTN的接触孔被填充。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2012231148A

公开(公告)日：2012-11-22

申请号：JP2012126848

申请日：2012-06-04

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANAKA TSUTOMU ,  YAMADA YASUHIRO ,  TAKEDA HIROHISA

IPC: H01L23/522 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L29/786 ,  H01L51/50

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device allowing implementation of a contact structure usable for connecting wires on three or more layers with the highest degree of efficiency by making use of a minimum area, and also provide a manufacturing method thereof and a display apparatus.SOLUTION: On a substrate 201, n conductive layers 202-204 with n equal to or larger than three are created as stacked layers and connected through a contact pattern. A main contact area in which the contact pattern is created includes (n-1) connection areas 211, 212 for connecting (n-1) conductive layers 202, 203. Of the (n-1) conductive layers, the conductive layers upper than the first layer in the direction of stacking on the substrate 201 (the direction normal to the principal plane of the substrate 201) are created such that the end part thereof faces a portion of the edge of the contact pattern CPTN. The (n-1) conductive layers are connected electrically by the nth conductive layer. The nth conductive layer is created to fill up a contact hole serving as the contact pattern CPTN.

Abstract translation: 要解决的问题：提供一种半导体器件，其允许实现用于通过利用最小面积以最高效率的三层或更多层连接导线的接触结构，并且还提供其制造方法和 显示装置。 解决方案：在衬底201上，n等于或大于3的n个导电层202-204被形成为堆叠层并通过接触图案连接。 形成接触图案的主要接触区域包括用于连接（n-1）个导电层202,203的（n-1）个连接区域211,212。在（n-1）个导电层中，导电层高于 产生在基板201上的堆叠方向上的第一层（与基板201的主平面垂直的方向），使得其端部面向接触图案CPTN的边缘的一部分。 （n-1）导电层由第n导电层电连接。 产生第n导电层以填充用作接触图案CPTN的接触孔。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2009130180A

公开(公告)日：2009-06-11

申请号：JP2007304357

申请日：2007-11-26

Applicant: Sony Corp ,  Sony Mobile Display Corp ,  ソニーモバイルディスプレイ株式会社 ,  ソニー株式会社

Inventor： NAGASAWA KOICHI ,  YAMAGUCHI TAKASHI ,  OZAKI YASUNAO ,  KANETANI YASUHIRO ,  TAKEDA HIROHISA ,  MIKAMI YASUO ,  MUTO KEISHI

IPC: H01L29/786 ,  G03F7/38 ,  G03F7/40

CPC classification number: H01L29/78633 ,  G02F1/133555 ,  G02F1/13394 ,  G02F1/136227 ,  H01L27/1248

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic apparatus that cures a resist pattern while maintaining a shape just after lithography without deteriorating characteristics of a thin film transistor covered with the resist pattern. SOLUTION: The method of manufacturing the electronic apparatus in which a resist pattern 24 is provided on a first transistor 1 comprising a thin film transistor Tr, includes the steps: of applying and forming a resist film 22 on the first substrate while covering the thin film transistor Tr; and of forming the resist pattern 24 by performing exposing and developing processing upon the resist film 22. Dry processing is then performed upon the first substrate 1 in which the resist pattern 24 is formed. While a channel part ch of the thin film transistor Tr is prevented from being irradiated with light of a shorter wavelength than a wavelength 260 nm, the resist pattern 24 after dry processing is irradiated thereafter at least either ultraviolet rays or visible light under a dry environment. The resist pattern 24 is then thermoset. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造电子设备的方法，该电子设备固化抗蚀剂图案，同时保持光刻之后的形状，而不会降低被抗蚀剂图案覆盖的薄膜晶体管的特性。 解决方案：制造其中在包括薄膜晶体管Tr的第一晶体管1上设置抗蚀剂图案24的电子设备的方法包括以下步骤：在第一衬底上施加和形成抗蚀剂膜22，同时覆盖 薄膜晶体管Tr; 并且通过对抗蚀剂膜22进行曝光和显影处理来形成抗蚀剂图案24.然后，在形成抗蚀剂图案24的第一基板1上进行干法处理。 虽然防止薄膜晶体管Tr的沟道部分ch被比波长比波长260nm短的光照射，然后在干燥处理后的抗蚀剂图案24在干燥环境下至少照射紫外线或可见光 。 然后抗蚀剂图案24被热固化。 版权所有（C）2009，JPO＆INPIT