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公开(公告)号：JP2003115594A
公开(公告)日：2003-04-18
申请号：JP2001310560
申请日：2001-10-05
Inventor： TANAKA TSUTOMU , MANO MICHIO , TORIYAMA SHIGETAKA , FUJINO MASAHIRO , KOMATSU HIROSHI , TAKEDA HIROHISA
IPC: G02F1/1368 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/308 , H01L29/786
Abstract: PROBLEM TO BE SOLVED: To improve the yield of a product by preventing defects in gate breakdown strength in a bottom gate type TFT. SOLUTION: The manufacturing method of a bottom gate type TFT 100A includes a step (1) of forming a gate electrode on a substrate, a step (2) of forming a gate insulating film on the gate electrode 2, a step (3) of forming a laminate made up of an protective insulating film 8 having a film thickness of 100 nm or smaller while an active-layer antecedent film (polysilicon film 7) and the protective insulating film 8 are laminated on the gate insulating film, a step (4) of implanting a dopant in an LDD region or in a source/drain region of the active-layer precursor film 8 through the protective insulating film 8, a step (5) of activating the implanted dopant and causing the other non-dopant part to be an active layer, a step (6) of modifying the quality of all or part of the protective insulating film 8, a step (7) of forming an interlayer insulating film on the modified protective insulating film 8, and a step (8) of forming a source/drain electrode on the interlayer insulating film.
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公开(公告)号：JP2006229081A
公开(公告)日：2006-08-31
申请号：JP2005043183
申请日：2005-02-18
Inventor： OKADA MOTONARI , TORIYAMA SHIGETAKA
IPC: H01L29/786 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L27/04
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which electrostatic discharge damage of a thin film transistor can be suppressed and reliability is enhanced, and to provide its manufacturing process.
SOLUTION: In the semiconductor device having a circuit formed of a plurality of thin film transistors 100, a gate interconnect line 22 connected commonly with a plurality of thin film transistors 100 is divided and the divided gate interconnect lines 22 are connected electrically through a connection interconnect line 29 arranged on an upper layer of the gate interconnect line 22.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供可以抑制薄膜晶体管的静电放电损坏并提高可靠性的半导体器件，并提供其制造工艺。 解决方案：在具有由多个薄膜晶体管100形成的电路的半导体器件中，与多个薄膜晶体管100共同连接的栅极互连线22被划分，并且划分的栅极互连线22电连接 布置在栅极互连线22的上层上的连接互连线29.版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2005223034A
公开(公告)日：2005-08-18
申请号：JP2004027575
申请日：2004-02-04
Inventor： NOZU DAISUKE , HAYASHI MUNEHARU , TORIYAMA SHIGETAKA
IPC: G02F1/1343 , H01L21/768 , H01L23/522
Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure which prevents a crack in an inter-layer insulating layer made of SOG.
SOLUTION: The wiring structure comprises a substrate insulating layer 20, a wiring layer 21 formed on the substrate insulating layer 20, and the SOG inter-layer insulating layer 23 formed on the substrate insulating layer 20 and the wiring layer 21. When the height of the top face of the inter-layer insulating layer 23 from the top face of the substrate insulating layer 20 is H
1 (m) and the same from the top face of the wiring layer 21 is H
2 (m), the wiring structure satisfies the following inequalities: H
1 -6 m, and H
2 ≥4×10
-7 m.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供一种防止由SOG制成的层间绝缘层中的裂纹的布线结构。 解决方案：布线结构包括基板绝缘层20，形成在基板绝缘层20上的布线层21和形成在基板绝缘层20和布线层21上的SOG层间绝缘层23.当 层间绝缘层23的顶面与基板绝缘层20的顶面的高度为H
1（m），并且与布线层21的顶面相同 H 2 （m），布线结构满足以下不等式：H 1 <3.0×10 -6 m，H 2 ≥4×10 -7 米。 版权所有（C）2005，JPO＆NCIPI -
公开(公告)号：JP2005148424A
公开(公告)日：2005-06-09
申请号：JP2003386087
申请日：2003-11-17
Inventor： TERANISHI YASUYUKI , NAKAJIMA YOSHIHARU , NOZU DAISUKE , HAYASHI MUNEHARU , TORIYAMA SHIGETAKA , SAKAI EIJI
Abstract: PROBLEM TO BE SOLVED: To effectively avoid a decrease in quality of a display image resulting from a subpixel having small areas in a multibit memory type display device by applying the present invention to a liquid crystal display device that, for example, has each pixel formed of a plurality of subpixels and represents gradations by driving the plurality of subpixels.
SOLUTION: Regarding subpixels 32AA and 32AB with small areas at parts 43A to 43E for display, the parts 43A and 43B for display are formed in a nearly square shape.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：为了有效地避免通过将本发明应用于例如具有多个存储器型显示装置的液晶显示装置的多位存储器型显示装置中由具有小面积的子像素产生的显示图像的质量的降低 每个像素由多个子像素形成，并且通过驱动多个子像素来表示灰度。
解决方案：关于用于显示的部分43A至43E具有小面积的子像素32AA和32AB，用于显示的部分43A和43B形成为几乎正方形的形状。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2004020573A
公开(公告)日：2004-01-22
申请号：JP2002170987
申请日：2002-06-12
Inventor： HAYASHI HISAO , TORIYAMA SHIGETAKA
IPC: G02F1/1339 , G02F1/1333 , G02F1/1368
Abstract: PROBLEM TO BE SOLVED: To improve the reliability of a liquid crystal display by reducing parasitic capacitance and preventing a liquid crystal from sticking to an electrode. SOLUTION: The liquid crystal display and a method for manufacturing the same comprise the steps of: sticking a counter substrate 15 and a substrate 1 of the driving side to each other via a sealing agent; and sealing a liquid crystal onto a region inside the position of the sealing agent. In the region on which the liquid crystal is sealed, an insulating material (a protective film 8) with a dielectric constant lower than that of the liquid crystal is provided on an electrode 5S other than a pixel driving electrode (a pixel electrode 10) with a height nearly equal to a gap depth into which the liquid crystal is sealed. An organic material may also be used as the insulating material. COPYRIGHT: (C)2004,JPO
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Patent Agency Ranking
公开(公告)号：JP2011146410A
公开(公告)日：2011-07-28
申请号：JP2010003575
申请日：2010-01-12
Inventor： OZEKI YOSHITAKA , KUWAHARA YASUTO , TORIYAMA SHIGETAKA , IKEDA HIROYUKI
IPC: H01L29/786 , G02F1/1368 , G09F9/30 , H01L21/336
CPC classification number: H01L29/78696 , G02F1/13624 , G02F1/136286 , H01L29/42384 , H01L29/78609 , H01L29/78645
Abstract: PROBLEM TO BE SOLVED: To provide a display device for simultaneously suppressing OFF current characteristics of a field effect transistor used for a switching circuit for driving pixels and improving ON current characteristics and improving an image quality by improving performance of the switching circuit. SOLUTION: In the switching circuit including one field effect transistor or a plurality of field effect transistors connected in series electrically, at least partial width of a semiconductor layer 15 serving as a channel of at least one field effect transistor is changed continuously in the direction of channel length. For example, width of a part at a source side of the semiconductor layer 15 in the channel section is decreased linearly from W 50 to W 51 and width of other parts is fixed to W 51 . COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供一种用于同时抑制用于驱动像素的开关电路的场效应晶体管的截止电流特性并提高导通电流特性并且通过改进开关电路的性能来提高图像质量的显示装置。 解决方案：在包括串联电连接的一个场效应晶体管或多个场效应晶体管的开关电路中，用作至少一个场效应晶体管的沟道的半导体层15的至少部分宽度连续地变化 渠道长度方向。 例如，沟道部中的半导体层15的源极侧的部分的宽度从W
50 线性地降低到W 51 ，其他部分的宽度固定 到W 51 。 版权所有（C）2011，JPO＆INPIT -
公开(公告)号：JP2005070360A
公开(公告)日：2005-03-17
申请号：JP2003299266
申请日：2003-08-22
Inventor： TORIYAMA SHIGETAKA
IPC: G02F1/1343 , G02F1/13 , G02F1/1345 , G09F9/00 , G09F9/30 , H01L21/60 , H01L23/498 , H05K1/03 , H05K3/40
CPC classification number: H01L24/83 , G02F1/13452 , H01L23/49816 , H01L23/49822 , H01L24/29 , H01L24/81 , H01L2224/16 , H01L2224/81801 , H01L2224/83192 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0106 , H01L2924/0781 , H01L2924/14 , H01L2924/3011 , H05K1/0306 , H05K3/4007 , H05K2201/0367 , H05K2201/099 , H05K2201/10674 , H05K2203/1189
Abstract: PROBLEM TO BE SOLVED: To connect an IC or a semiconductor chip with a high reliability. SOLUTION: An electrode part 20 to which the metal electrode (bump) of an IC circuit will be connected from an upper part is formed on the glass substrate 11 of a liquid crystal display device. The electrode part 20 is constituted by opening an inter-layer insulating film 23 in a part corresponding to metal wiring 22 and forming a land-like electrode pad 25 in this opened part. In the present invention, the plane shape of the electrode pad 25 is made smaller than the opened part of the inter-layer insulating film 23. Thus the flatness of the peripheral surface of the electrode 20 is improved. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：以高可靠性连接IC或半导体芯片。 解决方案：在液晶显示装置的玻璃基板11上形成有从上部连接有IC电路的金属电极（凸块）的电极部20。 电极部20通过在对应于金属布线22的部分中打开层间绝缘膜23并在该开口部分形成台状电极焊盘25而构成。 在本发明中，使电极焊盘25的平面形状比层间绝缘膜23的开放部分小。因此，电极20的周面的平坦性提高。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2010122695A
公开(公告)日：2010-06-03
申请号：JP2009292101
申请日：2009-12-24
Inventor： TERANISHI YASUYUKI , NAKAJIMA YOSHIHARU , NOZU DAISUKE , HAYASHI MUNEHARU , TORIYAMA SHIGETAKA , SAKAI EIJI
IPC: G09F9/30 , G02F1/133 , G02F1/1343 , G09G3/20 , G09G3/36
Abstract: PROBLEM TO BE SOLVED: To effectively avoid deterioration in the quality of a displayed image caused by a sub-pixel of a small area in a display device employing a multibit memory system by applying the display device to a liquid crystal display, for example, having a pixel composed of a plurality of sub-pixels and employing a system of representing a grayscale level by driving the plurality of sub-pixels.
SOLUTION: In sub-pixels 32AA, 32AB which are small in areas of regions 43A to 43E to be displayed, the regions 43A, 43B to be displayed are formed into approximately square shapes.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：为了有效地避免通过将显示装置应用于液晶显示器而使用多位存储器系统的显示装置中由小区域的子像素引起的显示图像质量的劣化，为 例如，具有由多个子像素组成的像素，并且采用通过驱动多个子像素来表示灰度级的系统。 解决方案：在要显示的区域43A至43E的区域中较小的子像素32AA，32AB中，要显示的区域43A，43B形成为近似正方形的形状。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2006030502A
公开(公告)日：2006-02-02
申请号：JP2004208039
申请日：2004-07-15
Inventor： WATANABE YASUHIRO , TORIYAMA SHIGETAKA , FUJIOKA TAKAYUKI , TAKAHASHI KENJI
IPC: G09F9/30 , G02F1/1368 , H01L21/3205 , H01L23/52 , H01L29/786
Abstract: PROBLEM TO BE SOLVED: To provide a display apparatus wherein parasitic capacitance formed between a driving side substrate and a counter side substrate is reduced, waveform distortion or delay of signals caused by the parasitic capacitance is eliminated, and load on an external driving IC can be reduced, and to provide its manufacturing method. SOLUTION: When the display apparatus has a wiring structure wherein signal lines 33 (33R, 33G, 33B, 33P) are wired in an area on a glass substrate 41 (driving side substrate) opposing to a second glass substrate (counter side substrate) 42, a recessed part 45 is formed on an oxide film 43 on the glass substrate 41 and the signal lines 33 are wired in the recessed part 45. Thus, the distance between a transparent electrode 44 and the signal lines 33 is increased, and the parasitic capacitance generated between the transparent electrode 44 and the signal lines 33 is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：为了提供一种显示装置，其中形成在驱动侧基板和对侧基板之间的寄生电容减小，消除了由寄生电容引起的信号的波形失真或延迟，并且外部驱动 可以减少IC，并提供其制造方法。 解决方案：当显示装置具有其中信号线33（33R，33G，33B，33P）被布线在玻璃基板41（驱动侧基板）上与第二玻璃基板（相对侧）相对的区域中的布线结构 基板）42，在玻璃基板41上的氧化膜43上形成有凹部45，并且信号线33被布线在凹部45中。因此，透明电极44与信号线33之间的距离增加， 并且在透明电极44和信号线33之间产生的寄生电容减小。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2005300579A
公开(公告)日：2005-10-27
申请号：JP2004111914
申请日：2004-04-06
Inventor： YAMAGAMI HIROYUKI , TERANISHI YASUYUKI , NAKAJIMA YOSHIHARU , NOZU DAISUKE , HAYASHI MUNEHARU , TORIYAMA SHIGETAKA , SAKAI EIJI
IPC: G02F1/1343 , G02F1/1368 , G09F9/30 , G09G3/20 , G09G3/36
CPC classification number: G09G3/3607
Abstract: PROBLEM TO BE SOLVED: To solve the problem that complication of layout is increased due to increase of the number of wirings and opening ratio of a pixel is reduced when a pixel electrode of a unit pixel is divided into more sub pixel electrodes for improving deviation of a center of gravity of sub pixel electrodes or complicated layout of the sub pixel electrodes is adopted, in an active matrix type liquid crystal display wherein gradation is expressed by an area gradation method. SOLUTION: In the active matrix type liquid crystal display wherein gradation is expressed by the area gradation method, layouts each having a plurality of sub pixel electrodes 31 to 35 are made upside-down for every one unit pixel e.g. in the horizontal direction, so that the layouts each having the plurality of sub pixel electrodes 31 to 35 are made different between unit pixels adjacent to each other in the horizontal direction, and the layouts each having the plurality of sub pixel electrodes 31 to 35 are made irregular between the adjacent unit pixels. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题为了解决由于布线数量的增加而引起的布局的复杂性增加的问题，并且当单位像素的像素电极被分成更多的子像素电极时，像素的开口率被分割 在通过区域灰度法表示灰度的有源矩阵型液晶显示器中，采用改善子像素电极的重心偏移或副像素电极的复杂布局。 解决方案：在通过区域灰度方法表示灰度的有源矩阵型液晶显示器中，对于每一个单位像素，各自具有多个子像素电极31至35的布局被颠倒。 在水平方向上使得具有多个子像素电极31至35的布局在水平方向上彼此相邻的单位像素之间不同，并且具有多个子像素电极31至35的布局是 在相邻单位像素之间形成不规则。 版权所有（C）2006，JPO＆NCIPI
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