公开(公告)号：JPH11102229A

公开(公告)日：1999-04-13

申请号：JP15315798

申请日：1998-06-02

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H

IPC: H01L21/8234 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  H01L27/088 ,  H03F1/30

Abstract: PROBLEM TO BE SOLVED: To reduce the supply voltage and standby current of the integrated circuit by generating the absolute value of the effective threshold voltage of only a selected MOSFET less than the absolute value of an initial threshold voltage and inhibiting a high standby current at this time. SOLUTION: Only the well of one MOSFET selected between MOSFETs 12 and 13 of the integrated circuit 10 is selectively biased. The MOSFETs 12 and 13 have initial threshold voltages. Selective bias operation generates the absolute value of the effective threshold voltage of only the selected MOSFET which is less than the absolute value of the initial threshold voltage and the high standby current to the integrated circuit 10 is inhibited. Therefore, the MOSFETs 12 and 13 can be operated with supply voltages lower than about 1 V.

公开(公告)号：JPH11111872A

公开(公告)日：1999-04-23

申请号：JP21785498

申请日：1998-07-31

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H ,  NGUYEN LOI

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To improve the insulation by providing an oxide layer having an increased thickness between the outer end of a polysilicon silicide layer and substrate disposed blow it. SOLUTION: A thin porous oxide is deposited at a comparatively low temp. to surround a polysilicon silicide layer 228, and this layer is anisotropically etched to form a pattern i.e., the lower corners 278 of a polysilicon layer 234 are rounded, compared with in prior art, to locate slightly apart from the top surface of an underlying n-type region 210 and the rounded corners are slightly laterally displaced from the boundary 276 of a side wall oxide spacer 230. These structures at the ends of a tunnel oxide layer 226 greatly improve the dielectric completeness at the lower corners of the polysilicon layer 228 by an oxidizing process for converting some of Si in the polysilicon layer 234 and a small amt. of the top surface of a substrate 206 into Si dioxide.

公开(公告)号：JPH1145948A

公开(公告)日：1999-02-16

申请号：JP14925298

申请日：1998-05-29

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU

IPC: H01L21/8244 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To enhance the operational characteristics of a cell while minimizing the geometry by constituting an SRAM memory cell of two storage transistors and two access transistors with four gates of these transistors being arranged all in the same direction. SOLUTION: Each set comprising four memory cells is arranged symmetrically to the source region 38 for each memory cell in a group. All gate electrodes formed of a first polysilicon layer are substantially parallel with each other and extend substantially linearly. Deviation from a line is less than one half of its own width and thereby lines 57, 59 can be located at an arbitrary position over one half of the width of gate electrode. Since linear and parallel storage transistors 12, 14 and word lines 32 are provided, operation of the cell is stabilized resulting in the enhancement of reliability and electric operation of a memory cell.

公开(公告)号：JPH1174378A

公开(公告)日：1999-03-16

申请号：JP17768898

申请日：1998-06-24

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  BRYANT FRANK RANDOLPH

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM(static random access memory) cell and the manufacture for reducing a memory area without degrading performance. SOLUTION: Two P type bulk silicon pull-down transistors 18 and 22 formed by two polysilicon layers, two N type active gate type pull-up TFTs(thin film transistors) 16 and 20, and two path gates 28 and 30, are mutually connected by four shared contacts 24 and 26. One polysilicon 1 of the polysilicon layers is turned to salicide and is provided with a gate electrode for the P type pull- down transistors 18 and 22, and the other polysilicon 2 is provided with a desired polysilicon 2 stringer disposed along the side part edge of the side part of the polysilicon 1 gate electrode and forms the channel area of the pull-up TFTs 16 and 20.