公开(公告)号：DE60308133T2

公开(公告)日：2007-08-09

申请号：DE60308133

申请日：2003-01-10

Applicant: ST MICROELECTRONICS NV ,  ST MICROELECTRONICS SRL

Inventor： CERISIER PATRICK ,  PANIGADA ANDREA

IPC: H03M3/02

Abstract: The device has an input terminal (BE) to receive a signal. Delta-sigma power amplification unit (MAP) comprises signal amplifiers respectively connected between the terminal and an adder (ADD). The adder is disposed between a frequency selector (INT1, INT2) and quantification unit. Values of the signal gain are adjusted in order to place zeros in a signal transfer function. An Independent claim is also included for a communication system.

公开(公告)号：DE60308133D1

公开(公告)日：2006-10-19

申请号：DE60308133

申请日：2003-01-10

Applicant: ST MICROELECTRONICS NV ,  ST MICROELECTRONICS SRL

Inventor： CERISIER PATRICK ,  PANIGADA ANDREA

IPC: H03M3/02

Abstract: The device has an input terminal (BE) to receive a signal. Delta-sigma power amplification unit (MAP) comprises signal amplifiers respectively connected between the terminal and an adder (ADD). The adder is disposed between a frequency selector (INT1, INT2) and quantification unit. Values of the signal gain are adjusted in order to place zeros in a signal transfer function. An Independent claim is also included for a communication system.

公开(公告)号：DE60312808D1

公开(公告)日：2007-05-10

申请号：DE60312808

申请日：2003-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CESURA GIOVANNI ,  PANIGADA ANDREA

IPC: H03M1/06 ,  H03M1/16 ,  H03M1/74

Abstract: A method of correction of the error in an output digital signal (Out) of an analog/digital converter (ADC) (100), in which said error is introduced by a multibit digital/analog converter (DAC) (125) incorporated in the ADC, comprises: providing a scrambling scheme (200) of input signals (th1-th8) to the DAC, the scrambling scheme defining a scrambling of the input signals in dependence of values of a group (R) of variables (r1-r7), to produce scrambled input signals (t1-t8); extrapolating from the scrambling scheme parameters (M-1) defining a transformation operated by the scrambling scheme on the input signals to obtain the scrambled input signals; assigning to the variables substantially uncorrelated values; on the basis of the parameters, of the substantially uncorrelated values and of the scrambled signals, calculating (905) coefficients (pj,pjrj) of a linear combination of vectors of a vector space, the linear combination of vectors corresponding to a vector of the vector space representative of the error introduced by the DAC; calculating (910-1,..., 910-7) the correlation of a signal (Res1d) containing the error introduced by the multibit DAC with each coefficient of the linear combination of vectors, to extract an estimation ( ) of each vector; on the basis of the coefficients and the estimations of the vectors, calculating a linear combination (pjrj ) representative of the estimation of the error introduced by the multibit DAC, and using the estimation of the error introduced by the DAC to correct the ADC output signal.

公开(公告)号：DE60310026D1

公开(公告)日：2007-01-11

申请号：DE60310026

申请日：2003-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CESURA GIOVANNI ,  PANIGADA ANDREA ,  BOSI ALESSANDRO

IPC: H03M1/06 ,  H03M1/16

Abstract: An analog-to-digital converter (200) with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution is proposed. The converter includes a plurality of stages (1053-1050) each one having means (110,115) for converting an analog local signal into a digital local signal with a local resolution lower than said resolution, means (120,125) for determining an analog residue indicative of a quantization error of the means for converting, and means (130) for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and further includes means (204) for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain. In the converter of the invention, the means for combining includes, for at least one of the stages (1053), means (205-240) for dynamically estimating a digital correction signal indicative of an analog error of the corresponding inter-stage gain, and means (230) for controlling the digital weight according to the digital correction signal.

公开(公告)号：DE60307226D1

公开(公告)日：2006-09-14

申请号：DE60307226

申请日：2003-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CESURA GIOVANNI ,  PANIGADA ANDREA ,  SERINA NADIA

IPC: H03M1/06 ,  H03M1/36 ,  H03M3/00 ,  H03M3/02 ,  H03M3/04

Abstract: An analog-to-digital converter (200) is proposed. The converter includes at least one stage (105) for converting an analog input signal into a digital output signal using a parallel quantizer (115) comparing the analog input signal with a plurality of threshold values in parallel; the converter of the invention further includes, for at least one selected stage (105), means (210,220) for estimating an analog correction signal indicative of the mean value of a quantization error of the selected stage, and means (440i) for at least partially compensating an offset error of the parallel quantizer (105) in the selected stage according to the analog correction signal.