公开(公告)号：ITTO20110414A1

公开(公告)日：2012-11-12

申请号：ITTO20110414

申请日：2011-05-11

Applicant: ST MICROELECTRONICS PVT LTD ,  ST MICROELECTRONICS SRL

Inventor： ALIPRANDI DAVIDE ,  FRAGNETO PASQUALINA ,  MAITI SRIJIB NARAYAN ,  PICCINELLI EMILIANO MARIO ,  ROSSI BEATRICE

公开(公告)号：DE602005020218D1

公开(公告)日：2010-05-12

申请号：DE602005020218

申请日：2005-07-28

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： SAHA KAUSHIK ,  SARKAR ABHIK ,  MAITI SRIJIB NARAYAN

IPC: H04N7/50 ,  G06T9/00

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.

公开(公告)号：DE60330834D1

公开(公告)日：2010-02-25

申请号：DE60330834

申请日：2003-11-10

Applicant: ST MICROELECTRONICS PVT LTD

Inventor： SAHA KAUSHIK ,  MAITI SRIJIB NARAYAN

IPC: H03H17/06 ,  G06F7/38 ,  H03H17/02

Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.