公开(公告)号：FR2823903A1

公开(公告)日：2002-10-25

申请号：FR0105403

申请日：2001-04-20

Applicant: ST MICROELECTRONICS SA

Inventor： FARCY ALEXIS ,  AMAL VINCENT ,  TORRES JOAQUIM

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L27/08 ,  H01P3/08 ,  H01Q1/36 ,  H01Q11/08 ,  H01Q13/20 ,  H01L27/00 ,  H01Q1/00

Abstract: The integrated chip inductance has a number of line conductors (L1 to L6) which are parallel and having an optimized width. Each line conductor is formed within the thickness of an isolating layer (20,23,27). The lines are interconnected by a perpendicular conductor segment.

公开(公告)号：FR2823377B1

公开(公告)日：2004-07-16

申请号：FR0104693

申请日：2001-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： TORRES JOAQUIM ,  AMAL VINCENT ,  FRACY ALEXIS

IPC: H01L21/3205 ,  H01L23/522 ,  H01L45/00

公开(公告)号：FR2813142B1

公开(公告)日：2002-11-29

申请号：FR0010697

申请日：2000-08-17

Applicant: ST MICROELECTRONICS SA

Inventor： AMAL VINCENT ,  TORRES JOAQUIM

IPC: H01L21/02 ,  H01G4/33 ,  H01L21/71

Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.

公开(公告)号：FR2823377A1

公开(公告)日：2002-10-11

申请号：FR0104693

申请日：2001-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： TORRES JOAQUIM ,  AMAL VINCENT ,  FRACY ALEXIS

IPC: H01L21/3205 ,  H01L23/522 ,  H01L45/00

Abstract: Formation of a conducting line (L) for high frequency or elevated currents, realized above a given part of a massive substrate (20) within which are formed other elements, comprises: (1) hollowing out a slice in the substrate; (2) forming an insulated zone (26) in the slice; and (3) forming the conducting line to the vertical of the insulated zone. An Independent claim is also included for a conducting line for high frequency or elevated currents in an integrated circuit chip.

公开(公告)号：FR2813142A1

公开(公告)日：2002-02-22

申请号：FR0010697

申请日：2000-08-17

Applicant: ST MICROELECTRONICS SA

Inventor： AMAL VINCENT ,  TORRES JOAQUIM

IPC: H01L21/02 ,  H01G4/33 ,  H01L21/71

Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.