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    GUARD INTERVAL OCCURRENCE IN DMT MODULATION TECHNIQUE
    1.
    发明专利
    GUARD INTERVAL OCCURRENCE IN DMT MODULATION TECHNIQUE 失效

    公开(公告)号：JP2000224138A

    公开(公告)日：2000-08-11

    申请号：JP2000017221

    申请日：2000-01-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MAZZONI SIMONE ,  CAMBONIE JOEL

    IPC: H04J11/00 ,  H04L27/26

    Abstract: PROBLEM TO BE SOLVED: To specially reduce a transmission delay by permitting a last sample forming a symbol before a shift to be placed at the beginning of the symbol, after the shift to directly form a prefix. SOLUTION: A complex coefficient Ai.ejϕi is added to an IFFT circuit 12 through a complex multiplier 22 in the case that i belongs to [1, N]. The N coefficients eiKiτ are respectively added to the second input of the multiplier 22 in correspondence. The IFFT circuit outputs a first sample S1' of the symbol Dt' with a time t1 and a memory 24 stores the sample which is controlled in a writing mode. A multiplexer 16 is changed-over and selects the output of the circuit 12. The state of a circuit 10 is kept in a state without changes, until a time tτ. Thus, the samples from S1' to Sj' can be stored in the memory 24 and cyclic prefixes formed by S1' to Sj' are given to the output of the multiplexer 16.

    A compact turbo-decoder having high efficiency, comprises two sets of processors for computing in parallel the syndromes and for updating in parallel the block, respectively
    4.
    发明专利
    A compact turbo-decoder having high efficiency, comprises two sets of processors for computing in parallel the syndromes and for updating in parallel the block, respectively 未知

    公开(公告)号：FR2834146A1

    公开(公告)日：2003-06-27

    申请号：FR0116619

    申请日：2001-12-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEJEAN PHILIPPE ,  CAMBONIE JOEL

    IPC: H03M13/29 ,  H04L1/00

    Abstract: The method for decoding the data encoded by blocks by use of a turbo-code comprises the steps of implementing different algorithms so that at least two steps are suited for applying in parallel to different blocks of data. The steps comprise a first step for computing a syndrome and a second step for updating the block by use of the syndrome computed in the course of the first step. The first step is carried out on a first part of the first block, and the second step is carried out on a second part of the first block or a part of the second block. In the first step a set of n first processors (PROC1) is operated in parallel on n rows, respectively columns, of a block, and in the second step a set of m second processors (PROC2) is operated in parallel on m rows, respectively columns, of a block. A block of data is of dimension 32 x 32 and n = m = 16. The data are coded by a coding of type BCH or extended BCH, and the updating is by use of an algorithm of Berlekamp or Euclide followed by an algorithm of Chase-Pyndiah. The decoding circuit (20) is claimed and comprises the first set of processors (PROC1) for computing the syndromes in parallel, where each syndrome corresponds to a syndrome of a row, respectively column, of the first part of the first block of data, and the second set of processors (PROC2) for updating in parallel the rows, respectively columns, of the second part of the first block or a part of the second block of data. The decoding circuit also comprises a first group of memory stores (A) which includes the random-access memories (RAM1,RAM1',RAM1'',RAM1''') including two optional (RAM10,RAM10') with access along rows, which can store at least two successive blocks of data, a second group of memory stores (B) including the random-access memories (RAM12,RAM13) as the working memory, a fourth group of memory stores (D) including the random-access memories (RAM14,RAM15) as the working memory or the buffer memory, a random-access memory (RAM18) for storing a block after processing and an optional FORMAT module connected to output (OUT'), a processing block 922) at input (IN') with a depuncturing module (DEPUNC), a bus (25), and a controller (27). Each memory store has a direct access to the bus. The decoding circuit allows to carry out 4 consecutive iterations in real time for the data flow rate of up to 54 Mbit/s and the blocks of dimension 32x32.

    5.
    发明专利
    未知

    公开(公告)号：FR2788907B1

    公开(公告)日：2001-04-13

    申请号：FR9901062

    申请日：1999-01-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： MAZZONI SIMONE ,  CAMBONIE JOEL

    IPC: H04J11/00 ,  H04L27/26 ,  H04J13/00

    Abstract: The circuit takes a sample from the header and re-copies this at the end of the signal. The circuit generates a cyclical symbol prefix composed of a series of samples in the time domain. The prefix is the reproduction of the last symbol samples in the symbol header. The symbol is obtained by inverse Fourier transformation of the complex coefficients corresponding to the respective frequencies. The circuit includes a device (22) for dephasing each complex coefficient of a value proportional to its frequency. A memory (24) is provided for storing the samples of the start of the symbol, and a further circuit (16) is provided for re-copying the memorised samples at the end of the symbol.

    7.
    发明专利
    未知

    公开(公告)号：FR2794921A1

    公开(公告)日：2000-12-15

    申请号：FR9907495

    申请日：1999-06-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

    IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26 ,  H04L27/32

    Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

    8.
    发明专利
    未知

    公开(公告)号：FR2788907A1

    公开(公告)日：2000-07-28

    申请号：FR9901062

    申请日：1999-01-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： MAZZONI SIMONE ,  CAMBONIE JOEL

    IPC: H04J11/00 ,  H04L27/26 ,  H04J13/00

    Abstract: The circuit takes a sample from the header and re-copies this at the end of the signal. The circuit generates a cyclical symbol prefix composed of a series of samples in the time domain. The prefix is the reproduction of the last symbol samples in the symbol header. The symbol is obtained by inverse Fourier transformation of the complex coefficients corresponding to the respective frequencies. The circuit includes a device (22) for dephasing each complex coefficient of a value proportional to its frequency. A memory (24) is provided for storing the samples of the start of the symbol, and a further circuit (16) is provided for re-copying the memorised samples at the end of the symbol.

    9.
    发明专利
    未知

    公开(公告)号：FR2772950B1

    公开(公告)日：2000-03-17

    申请号：FR9716115

    申请日：1997-12-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAMBONIE JOEL

    IPC: G06F17/14 ,  G06F9/38

    Abstract: Device is characterised in that it comprises a first stage of treatment of a radix equal to 4 including an element by element processing step for carrying out the Fourier transforms on elementary parts equal to 4 on data blocks. Also included is a means for memorising the elements including a random access memory, especially a direct access memory.

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