公开(公告)号：FR2794921A1

公开(公告)日：2000-12-15

申请号：FR9907495

申请日：1999-06-14

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26 ,  H04L27/32

Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

公开(公告)号：DE60021479T2

公开(公告)日：2006-05-24

申请号：DE60021479

申请日：2000-05-25

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  H04L27/26 ,  G06T1/60 ,  H04J11/00

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.

公开(公告)号：DE60021479D1

公开(公告)日：2005-09-01

申请号：DE60021479

申请日：2000-05-25

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  G06T1/60 ,  H04J11/00 ,  H04L27/26

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.

公开(公告)号：FR2794598B1

公开(公告)日：2001-09-21

申请号：FR9906963

申请日：1999-06-02

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  G06T1/60 ,  H04J11/00 ,  H04L27/26 ,  H04L27/32

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.

公开(公告)号：FR2794921B1

公开(公告)日：2001-09-14

申请号：FR9907495

申请日：1999-06-14

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26 ,  H04L27/32

Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

公开(公告)号：DE60019367D1

公开(公告)日：2005-05-19

申请号：DE60019367

申请日：2000-05-26

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26

Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

公开(公告)号：FR2794598A1

公开(公告)日：2000-12-08

申请号：FR9906963

申请日：1999-06-02

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  G06T1/60 ,  H04J11/00 ,  H04L27/26 ,  H04L27/32

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.