公开(公告)号：JP2000330791A

公开(公告)日：2000-11-30

申请号：JP2000134658

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： BERNARD BRUNO ,  GROSSIER NICOLAS ,  DABBAGH AHMED

IPC: G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To improve the controllability of access to a memory by comparing an address of an address storage queue with a received load address and selecting the operation order of saving operation and loading operation. SOLUTION: A comparator 84 compares X-memory load address inputs 140 and 141 with all effective inputs 182 of the address storage queue SAQX 143. When a matching input is found, a control circuit 160 supplies a signal to a selector 181. The output 182 from the address storage queue 143 becomes effective and is varied in numeral at a memory position before loading operation. The load addresses of the inputs 140 and 141 are arranged in an address load queue LAQX 145. When no match is found, the control circuit 160 operates the selector 181 to obtain an output 183 from the load address inputs 140 and 141 before the address storage queue output 182. The loading operation is carried out in a single cycle while evading the queue 145.