公开(公告)号：JP2000330791A

公开(公告)日：2000-11-30

申请号：JP2000134658

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： BERNARD BRUNO ,  GROSSIER NICOLAS ,  DABBAGH AHMED

IPC: G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To improve the controllability of access to a memory by comparing an address of an address storage queue with a received load address and selecting the operation order of saving operation and loading operation. SOLUTION: A comparator 84 compares X-memory load address inputs 140 and 141 with all effective inputs 182 of the address storage queue SAQX 143. When a matching input is found, a control circuit 160 supplies a signal to a selector 181. The output 182 from the address storage queue 143 becomes effective and is varied in numeral at a memory position before loading operation. The load addresses of the inputs 140 and 141 are arranged in an address load queue LAQX 145. When no match is found, the control circuit 160 operates the selector 181 to obtain an output 183 from the load address inputs 140 and 141 before the address storage queue output 182. The loading operation is carried out in a single cycle while evading the queue 145.

公开(公告)号：GB2362968B

公开(公告)日：2003-12-10

申请号：GB9930589

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO ,  WOJCIESZAK LAURENT ,  DEHAMEL ARNAUD

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/07

公开(公告)号：GB2362968A

公开(公告)日：2001-12-05

申请号：GB9930589

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO ,  WOJCIESZAK LAURENT ,  DEHAMEL ARNAUD

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/07

Abstract: A system for executing instructions having assigned guard or prediction indicators, the system comprising instruction supply circuitry, at least one pipelined execution unit for receiving instructions from the supply circuitry together with a guard or prediction indicator selected from a set of guard or prediction indicators. The execution unit includes a master guard value store containing master values for the guard indicators and circuitry for resolving the guard or prediction value of the guard or prediction indicator in the instruction pipeline and providing a signal to indicate if the pipeline is committed to executing the instruction. The system includes an emulator which has watch circuitry for watching selected instructions in the execution pipeline and synchronising circuitry for correlating resolution of the guard or prediction indicator of each selected instruction with a program count for that instruction.

公开(公告)号：GB2362729B

公开(公告)日：2004-02-11

申请号：GB9930588

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO

IPC: G06F9/38

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

公开(公告)号：GB2362729A

公开(公告)日：2001-11-28

申请号：GB9930588

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO

IPC: G06F9/38

Abstract: A system for executing pipelined instructions, the system including instruction fetch circuitry, instruction dispatch circuitry, data memory for use in store and load operations, data memory access circuitry and emulator circuitry for use in debug operations. The emulator circuitry includes circuitry indicating an error in the data memory access operation, snoop circuitry for snooping memory access in the data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with program counts for the instructions associated with the access addresses and memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.