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公开(公告)号：JP2000330791A
公开(公告)日：2000-11-30
申请号：JP2000134658
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： BERNARD BRUNO , GROSSIER NICOLAS , DABBAGH AHMED
Abstract: PROBLEM TO BE SOLVED: To improve the controllability of access to a memory by comparing an address of an address storage queue with a received load address and selecting the operation order of saving operation and loading operation. SOLUTION: A comparator 84 compares X-memory load address inputs 140 and 141 with all effective inputs 182 of the address storage queue SAQX 143. When a matching input is found, a control circuit 160 supplies a signal to a selector 181. The output 182 from the address storage queue 143 becomes effective and is varied in numeral at a memory position before loading operation. The load addresses of the inputs 140 and 141 are arranged in an address load queue LAQX 145. When no match is found, the control circuit 160 operates the selector 181 to obtain an output 183 from the load address inputs 140 and 141 before the address storage queue output 182. The loading operation is carried out in a single cycle while evading the queue 145.
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公开(公告)号：DE69930235D1
公开(公告)日：2006-05-04
申请号：DE69930235
申请日：1999-05-03
Applicant: ST MICROELECTRONICS SA
Inventor： ALOFS THOMAS , GROSSIER NICOLAS
Abstract: A circuit for controlling the storage of data in a memory element has: a) a bistable device (22) having a first input for receiving an address input (24) and a second input (26) for receiving a clock signal; and b) circuitry (30) for receiving the output of the bistable device (22) and the clock signal (26) and providing a write enable signal for said memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, said first and next transitions being in the same clock cycle.
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