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    MEMORY DEVICE AND INTEGRATED CIRCUIT
    1.
    发明专利
    MEMORY DEVICE AND INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：JP2003152119A

    公开(公告)日：2003-05-23

    申请号：JP2002252983

    申请日：2002-08-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

    IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide an FAMOS memory location which can have at least three completely natural program levels. SOLUTION: An FAMOS memory location is provided with a single floating gate (GR) overlapping the active plane of a semiconductor substrate along contour (PF1, PF2) of at least two asymmetric overlaps in order to determine at least two electrodes in an active region. A memory location program means (MC, SW) applies a set of specified different voltages selectively to the electrodes such that at least three program logical levels are outputted to the memory location.

    Memory device which is electrically programmable in an irreversible manner, comprises matrix of memory cells, each with a transistor and a capacitor with destructible dielectric
    3.
    发明专利
    Memory device which is electrically programmable in an irreversible manner, comprises matrix of memory cells, each with a transistor and a capacitor with destructible dielectric 未知

    公开(公告)号：FR2840444A1

    公开(公告)日：2003-12-05

    申请号：FR0206651

    申请日：2002-05-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CASPAR DANIEL

    IPC: G11C8/02 ,  G11C17/16 ,  G11C17/14 ,  H01L27/115

    Abstract: The memory device comprises a memory matrix (MM) of memory cells (CLij), each comprising an access transistor and a capacitor whose dielectric is compatible with a technology of type dynamic random-access memory (DRAM). Each row comprises a group of cells (CLi) whose gates of transistors are connected together by a first metallization (WLAi), and whose upper electrodes (ES) of capacitors are connected together by a second metallization (WLPi). Each column comprises a group of cells (CLj) whose sources of transistors are connected together by a third metallization (BLj). The memory control means (MCM) can apply the chosen voltages to the first, second and third metallizations in a manner to program selectively only one cell by breaking down its dielectric without programming other cells and without breaking down the transistors of all cells. A memory cell (CLij) is programmed by applying a gate voltage (Vg) to the first metallization (WLAi), and by applying a voltage difference sufficient to break down the dielectric of capacitor to the second (WLPi) and third (BLj) metallizations; the voltages applied to other metallizations are designed so to block the transistors of other cells of the memory matrix. The transistors of cells are of type n-MOS. The memory control means can apply the chosen voltages to the first, second and third metallizations in a manner to read selectively the logic contents of only one memory cell (CLij) without reading the contents of other memory cells. The memory device (claimed) is implemented in the form of an integrated circuit.

    5.
    发明专利
    未知

    公开(公告)号：DE60330130D1

    公开(公告)日：2009-12-31

    申请号：DE60330130

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    6.
    发明专利
    未知

    公开(公告)号：AT449424T

    公开(公告)日：2009-12-15

    申请号：AT03709915

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    7.
    发明专利
    未知

    公开(公告)号：FR2840444B1

    公开(公告)日：2005-04-01

    申请号：FR0206651

    申请日：2002-05-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CASPAR DANIEL

    IPC: G11C8/02 ,  G11C17/16 ,  G11C17/14 ,  H01L27/115

    Abstract: The memory device comprises a memory matrix (MM) of memory cells (CLij), each comprising an access transistor and a capacitor whose dielectric is compatible with a technology of type dynamic random-access memory (DRAM). Each row comprises a group of cells (CLi) whose gates of transistors are connected together by a first metallization (WLAi), and whose upper electrodes (ES) of capacitors are connected together by a second metallization (WLPi). Each column comprises a group of cells (CLj) whose sources of transistors are connected together by a third metallization (BLj). The memory control means (MCM) can apply the chosen voltages to the first, second and third metallizations in a manner to program selectively only one cell by breaking down its dielectric without programming other cells and without breaking down the transistors of all cells. A memory cell (CLij) is programmed by applying a gate voltage (Vg) to the first metallization (WLAi), and by applying a voltage difference sufficient to break down the dielectric of capacitor to the second (WLPi) and third (BLj) metallizations; the voltages applied to other metallizations are designed so to block the transistors of other cells of the memory matrix. The transistors of cells are of type n-MOS. The memory control means can apply the chosen voltages to the first, second and third metallizations in a manner to read selectively the logic contents of only one memory cell (CLij) without reading the contents of other memory cells. The memory device (claimed) is implemented in the form of an integrated circuit.

    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means
    10.
    发明专利
    Method for erasing memory cell of type FAMOS and corresponding memory-cell device, by electrical means 未知

    公开(公告)号：FR2823363A1

    公开(公告)日：2002-10-11

    申请号：FR0104621

    申请日：2001-04-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

    IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/14

    Abstract: The method is for electrical erasing of a memory cell (CM) of type FAMOS, which comprises a p-MOS transistor with a floating gate which is not connected. The erasing is by the application of determined voltages to the bulk (B), the source (S) and the drain (D) of the transistor by an erasing module (MEF), that is a voltage VB to the bulk, which is higher than at last 4-6 V, with still lower voltages VS and VD applied to the source and the drain, respectively, and below a limiting voltage which causes the destruction of the cell, which is about 10 V. The difference between voltages applied to the source and the drain is non-null and positive, and below a predetermined threshold, which is about 1 V. For example, in the case of 0.18 micrometer technology, the source voltage is about 1 V, the drain voltage null, and the bulk voltage about 7-8 V, and the erasing takes about 1 minute. The difference between the source and the drain voltages is variable in the course of erasing process. The memory device comprises an electrically erasable memory cell (CM) of type FAMOS. The p-MOS transistor of the memory cell has a standard linear configuration, or more advantageously a ring ocnfiguration which comprises a central electrode surrounded by the gate and a peripheral electrode. The device comprises programming means for writing data into the memory cell, reading means for reading the content of the memory cell, and control means for selectively connecting the means for programming, reading and erasing of the memory cell. The device comprises several electrically erasable memory cells of type FAMOS. The memory device is a part of an integrated circuit.

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