公开(公告)号：JP2003273257A

公开(公告)日：2003-09-26

申请号：JP2003057906

申请日：2003-03-05

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which overcomes the data holding problem caused by the thinness of its grid dielectric present in the interface between its STI-type isolation region and its grid material.
SOLUTION: The semiconductor memory device comprises a non-volatile programmable and electrically erasable memory cell having a single layer of grid material. Also, the memory cell comprises a floating grid transistor and a control grid within an active semiconductor area which is formed in a region of a substrate and is delimited by an isolation region. The single layer of grid material wherein the floating grid is formed extends integrally above the active semiconductor area without overlapping part of the isolation region. The floating grid transistor is electrically isolated from the control grid by PN junctions that are inversely polarized.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种克服由其STI型隔离区域和其栅格材料之间的界面中存在的栅极电介质薄度引起的数据保持问题的存储器件。 解决方案：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储单元。 此外，存储单元包括浮动栅极晶体管和在有源半导体区域内的控制栅格，该有源半导体区域形成在衬底的区域中并由隔离区域限定。 其中形成浮栅的单层栅格材料在有源半导体区域上整体地延伸，而不与隔离区的重叠部分重叠。 浮栅晶体管通过PN极点与控制栅极电隔离，反向极化。 版权所有（C）2003，JPO

公开(公告)号：FR2896612A1

公开(公告)日：2007-07-27

申请号：FR0600554

申请日：2006-01-20

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  TESSIER JEAN MARC

IPC: G11C11/407 ,  H01L21/8247 ,  H01L27/115

Abstract: Ce dispositif de mémoire non-volatile comprend un réseau (9) de cellules de mémoire non-volatiles comportant chacune un transistor à grille flottante, ledit réseau de cellules étant destiné au stockage de données sous la forme d'un ensemble de mots de données.Il comporte en outre des moyens (12) de détection de pertes de charges pour détecter périodiquement une perte de charges stockées dans les cellules et des moyens pour reprogrammer les cellules pour lesquelles une perte de charges a été détectée de manière à rétablir le niveau de charges stockées.

公开(公告)号：FR2875352B1

公开(公告)日：2007-05-11

申请号：FR0409650

申请日：2004-09-10

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  FOURNEL RICHARD

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/09 ,  H03M13/19 ,  H03M13/35 ,  H03M13/37

Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

公开(公告)号：FR2896612B1

公开(公告)日：2008-06-27

申请号：FR0600554

申请日：2006-01-20

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  TESSIER JEAN MARC

IPC: G11C11/407 ,  H01L21/8247 ,  H01L27/115

Abstract: The device has an analog core (8) with a data control block (12) controlling operating modes of a memory and including a memory refreshing algorithm for periodically reprogramming non-volatile memory cells (9) subjected to a charge loss. The block (12) comprises an algorithm for decoding and reorganizing data bits in a redundant manner. The block (12) has a multiplexer which delivers 8 successive words of 8 bits to a 64 bit register from incident 8 bit word. The bits are delivered to a coding block (14) of an error correction block (13) including a hamming type error correction code. An independent claim is also included for a method of programming a non-volatile memory device.

公开(公告)号：FR2840444B1

公开(公告)日：2005-04-01

申请号：FR0206651

申请日：2002-05-30

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  CASPAR DANIEL

IPC: G11C8/02 ,  G11C17/16 ,  G11C17/14 ,  H01L27/115

Abstract: The memory device comprises a memory matrix (MM) of memory cells (CLij), each comprising an access transistor and a capacitor whose dielectric is compatible with a technology of type dynamic random-access memory (DRAM). Each row comprises a group of cells (CLi) whose gates of transistors are connected together by a first metallization (WLAi), and whose upper electrodes (ES) of capacitors are connected together by a second metallization (WLPi). Each column comprises a group of cells (CLj) whose sources of transistors are connected together by a third metallization (BLj). The memory control means (MCM) can apply the chosen voltages to the first, second and third metallizations in a manner to program selectively only one cell by breaking down its dielectric without programming other cells and without breaking down the transistors of all cells. A memory cell (CLij) is programmed by applying a gate voltage (Vg) to the first metallization (WLAi), and by applying a voltage difference sufficient to break down the dielectric of capacitor to the second (WLPi) and third (BLj) metallizations; the voltages applied to other metallizations are designed so to block the transistors of other cells of the memory matrix. The transistors of cells are of type n-MOS. The memory control means can apply the chosen voltages to the first, second and third metallizations in a manner to read selectively the logic contents of only one memory cell (CLij) without reading the contents of other memory cells. The memory device (claimed) is implemented in the form of an integrated circuit.

公开(公告)号：FR2838554B1

公开(公告)日：2004-07-09

申请号：FR0209454

申请日：2002-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

公开(公告)号：FR2837023B1

公开(公告)日：2004-05-28

申请号：FR0202853

申请日：2002-03-06

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：FR2838554A1

公开(公告)日：2003-10-17

申请号：FR0209454

申请日：2002-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

公开(公告)号：FR2929750A1

公开(公告)日：2009-10-09

申请号：FR0852353

申请日：2008-04-08

Applicant: ST MICROELECTRONICS SA

Inventor： CANDELIER PHILIPPE ,  GENDRIER PHILIPPE ,  DAMIENS JOEL ,  LE ROUX ELISE

IPC: G11C17/12 ,  G11C17/16

Abstract: Le circuit intégré comprend un dispositif de mémoire du type électriquement programmable de façon irréversible comportant plusieurs cellules-mémoires, chaque cellule-mémoire (CL) comportant une zone diélectrique (DX) disposée entre une première électrode et une deuxième électrode électriquement couplée à un transistor. Le dispositif de mémoire comporte en outre au moins un premier moyen de liaison électriquement conducteur (PML1), électriquement couplé aux premières électrodes (E1) d'au moins deux cellules-mémoires, ces deux premières électrodes (E1) étant destinées à être couplées à une même tension de polarisation (HV), le premier moyen de liaison (PML1) étant disposé sensiblement dans le même plan que les premières électrodes (E1) de ces deux cellules-mémoires.

公开(公告)号：FR2875352A1

公开(公告)日：2006-03-17

申请号：FR0409650

申请日：2004-09-10

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  FOURNEL RICHARD

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/09 ,  H03M13/19 ,  H03M13/35 ,  H03M13/37

Abstract: La mémoire stocke des blocs-codes comportant des données d'informations et des données de contrôle. Le procédé comprend une lecture de chaque élément d'un bloc-code comportant une comparaison du courant délivré par la cellule-mémoire stockant cet élément avec un courant de référence, et un décodage du bloc-code ainsi lu délivrant une information représentative du nombre d'erreurs dans le bloc-code lu. En présence d'un nombre d'erreurs supérieur à un,a) on modifie la valeur du courant de référence (Iref) d'un pas choisi, etb) on effectue de nouveau une lecture et un décodage du bloc-code de façon à obtenir une nouvelle information d'erreur, eton réitère éventuellement les phases a) et b) jusqu'à obtenir un nombre final d'erreurs au plus égal à un.En variante on peut modifier dans l'étape a) l'instant d'enregistrement des données lors de l'opération de lecture.