公开(公告)号：FR2830365B1

公开(公告)日：2004-12-24

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

公开(公告)号：FR2830365A1

公开(公告)日：2003-04-04

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.