公开(公告)号：DE60023770T2

公开(公告)日：2006-06-01

申请号：DE60023770

申请日：2000-02-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：DE60023770D1

公开(公告)日：2005-12-15

申请号：DE60023770

申请日：2000-02-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：FR2790345B1

公开(公告)日：2001-04-27

申请号：FR9902365

申请日：1999-02-25

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  H04L9/00

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：FR2790345A1

公开(公告)日：2000-09-01

申请号：FR9902365

申请日：1999-02-25

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  H04L9/00

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.