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    5.
    发明专利
    未知

    公开(公告)号：FR2840453A1

    公开(公告)日：2003-12-05

    申请号：FR0206870

    申请日：2002-06-04

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： LENOBLE DAMIEN ,  GUILMEAU ISABELLE

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

    Abstract: The fabrication of a MOS transistor comprises the production of extension source and drain regions incorporating the formation of a gate region on a semiconductor substrate and an implantation of doping agents either side and at a distance from the gate. The production of extension source and drain regions includes the formation of an intermediate layer (CI) on the sides of the gate (GR) and on the surface of the substrate. The intermediate layer is formed of a material less dense than silicon dioxide and the implantation of doping agents (IMP) is effected across the part of the intermediate layer situated on the substrate. An Independent claim is also included for an integrated circuit incorporating at least one transistor fabricated by this method.

    PROCEDE DE FORMATION DE TRANSISTORS MOS
    7.
    发明专利
    PROCEDE DE FORMATION DE TRANSISTORS MOS 未知

    公开(公告)号：FR2881875A1

    公开(公告)日：2006-08-11

    申请号：FR0550374

    申请日：2005-02-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENOBLE DAMIEN ,  LALLEMENT FABRICE

    IPC: H01L21/265 ,  H01L21/336

    Abstract: L'invention concerne un procédé de formation, dans un substrat semiconducteur monocristallin d'un premier type conductivité, de régions de surface dopées du second type de conductivité et de régions plus profondes dopées du premier type de conductivité sous-jacentes auxdites régions de surface, comprenant l'étape consistant à polariser négativement le substrat (41) placé au voisinage d'un plasma (43) comportant sous forme de cations des dopants du premier type de conductivité et des dopants d'un second type de conductivité, les dopants du second type de conductivité ayant une masse atomique supérieure à celle des dopants du premier type de conductivité.

    8.
    发明专利
    未知

    公开(公告)号：FR2840453B1

    公开(公告)日：2005-06-24

    申请号：FR0206870

    申请日：2002-06-04

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： LENOBLE DAMIEN ,  GUILMEAU ISABELLE

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

    Abstract: The fabrication of a MOS transistor comprises the production of extension source and drain regions incorporating the formation of a gate region on a semiconductor substrate and an implantation of doping agents either side and at a distance from the gate. The production of extension source and drain regions includes the formation of an intermediate layer (CI) on the sides of the gate (GR) and on the surface of the substrate. The intermediate layer is formed of a material less dense than silicon dioxide and the implantation of doping agents (IMP) is effected across the part of the intermediate layer situated on the substrate. An Independent claim is also included for an integrated circuit incorporating at least one transistor fabricated by this method.

    Fabrication of an integrated circuit incorporating a MOSFET with a reduced gate length
    9.
    发明专利
    Fabrication of an integrated circuit incorporating a MOSFET with a reduced gate length 未知

    公开(公告)号：FR2847383A1

    公开(公告)日：2004-05-21

    申请号：FR0214255

    申请日：2002-11-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENOBLE DAMIEN

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

    Abstract: Fabrication of an integrated circuit, incorporating a crystalline silicon substrate and a gate formed on the substrate, consists of: (a) treating a region of the substrate to obtain an amorphous silicon region; (b) implanting a doping species into a sub-region included in the region of the substrate to form some extensions of the drain and source; (c) forming of the drain and source at low temperature. An Independent claim is also included for an integrated circuit incorporating at least one transistor obtained by this method. The temperature used in the drain and source formation stage is less than 800 degrees C.

    10.
    发明专利
    未知

    公开(公告)号：FR2881875B1

    公开(公告)日：2007-04-13

    申请号：FR0550374

    申请日：2005-02-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENOBLE DAMIEN ,  LALLEMENT FABRICE

    IPC: H01L21/265 ,  H01L21/336

    Abstract: A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.

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