公开(公告)号：DE60000111T2

公开(公告)日：2002-10-31

申请号：DE60000111

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE-NOELLE

IPC: G06F7/52 ,  G06F7/72

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.

公开(公告)号：DE60000111D1

公开(公告)日：2002-05-16

申请号：DE60000111

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE-NOELLE

IPC: G06F7/52 ,  G06F7/72

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.