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    SINGLE CRYSTAL SUBSTRATE MANUFACTURING METHOD AND INTEGRATED CIRCUIT FORMED THEREON
    2.
    发明专利
    SINGLE CRYSTAL SUBSTRATE MANUFACTURING METHOD AND INTEGRATED CIRCUIT FORMED THEREON 审中-公开

    公开(公告)号：JP2002270509A

    公开(公告)日：2002-09-20

    申请号：JP2001394184

    申请日：2001-12-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/76 ,  H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L21/762 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861

    Abstract: PROBLEM TO BE SOLVED: To manufacture a single crystal substrate allowing a silicon epitaxial layer having no crystal defect to be formed thereafter. SOLUTION: The manufacturing method comprises a step of forming an initial single crystal substrate having at least one crystal lattice discontinuity locally on the surface, recessing the discontinuous spot of the initial substrate, making a crystal lattice around the recess amorphous, depositing a layer of an amorphous material having the same chemical composition as the initial substrate on an obtained structure, and thermally annealing the obtained structure to re-crystallize the amorphous portions so as to continue the single crystal lattice of the initial substrate.

    INTEGRATED CIRCUIT AND METHOD FOR MAKING SAME
    3.
    发明申请
    INTEGRATED CIRCUIT AND METHOD FOR MAKING SAME 审中-公开
    集成电路及其制作方法

    公开(公告)号：WO02056370A8

    公开(公告)日：2002-08-08

    申请号：PCT/FR0200054

    申请日：2002-01-09

    Applicant: ST MICROELECTRONICS SA ,  MENUT OLIVIER ,  GRIS YVON

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L27/146

    CPC classification number: H01L29/808 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/14683

    Abstract: In one particular embodiment, the integrated circuit comprises a load storing semiconductor device comprising at least a control transistor T and a storage capacitor TRC. The device comprises a substrate including a lower region containing at least a buried capacitive trench TRC forming said storage capacitor, a casing CS located above said lower region of the substrate. The control transistor T is produced in and on the casing and said capacitive trench is located beneath the transistor and is in contact with the casing.

    Abstract translation: 在一个具体实施例中，集成电路包括至少包括控制晶体管T和存储电容器TRC的负载存储半导体器件。 该器件包括：衬底，其包括至少包含形成所述存储电容器的掩埋电容沟槽TRC的下部区域，位于衬底的所述下部区域上方的壳体CS。 控制晶体管T产生在壳体中和壳体上，并且所述电容沟槽位于晶体管下方并与壳体接触。

    6.
    发明专利
    未知

    公开(公告)号：FR2819631A1

    公开(公告)日：2002-07-19

    申请号：FR0100414

    申请日：2001-01-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/76 ,  H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L21/762 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861

    Abstract: Semiconductor single crystal substrate is made by forming an initial single crystal substrate (1) having lattice discontinuity locally on its surface, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on the obtained structure, and thermally annealing, to recrystallize the amorphous material. Production of a semiconductor single crystal substrate involves: (a) Forming an initial single crystal substrate (1), then successively depositing on the initial substrate (1) a first layer (2) of a first material and a second layer (3) of a second material, and etching a trench (4) which is subsequently filled with a filling material and which forms a lattice discontinuity in the single crystal lattice; (b) Performing selective etching with respect to the second layer (3), the first layer (2) and an upper part of the filling material of the trench (4), so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer (3); (c) Amorphizing the single crystal lattice around the periphery of the recess; (d) Depositing a layer of amorphous material having the same chemical composition as that of the initial substrate (1) on the obtained structure; and (e) Thermally annealing the structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate. The initial substrate is selected from silicon, germanium, silicon carbide, gallium arsenide, and an alloy containing at least some of these materials. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Amorphization is self-aligned on the trench (4). Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit comprising a single crystal silicon substrate produced by the above process, and comprising at least two adjacent transistors produced in the body of the substrate that includes at least one buried trench forming an isolating trench separating the buried layers adjacent to the transistors.

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