公开(公告)号：FR2817417B1

公开(公告)日：2003-01-24

申请号：FR0015307

申请日：2000-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  NARCHE PASCAL ,  RUAT LUDOVIC

IPC: G01R31/317 ,  G06F11/22 ,  H03K21/38 ,  G06F11/30 ,  G06F13/00 ,  H03K19/003

公开(公告)号：FR2817417A1

公开(公告)日：2002-05-31

申请号：FR0015307

申请日：2000-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  NARCHE PASCAL ,  RUAT LUDOVIC

IPC: G01R31/317 ,  G06F11/22 ,  H03K21/38 ,  G06F11/30 ,  G06F13/00 ,  H03K19/003

Abstract: The microprocessor has a counter (CNTR) with a count input (E1) and a reset input (E2). The reset input is controlled by a signal (CS) present on a microprocessor pin (P2). The control signal is set either internally (R1) or externally to a logic value that ensures the counter reset is active during the initialization of the microprocessor.

公开(公告)号：DE60229115D1

公开(公告)日：2008-11-13

申请号：DE60229115

申请日：2002-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： NARCHE PASCAL

IPC: G06F12/14 ,  G11C16/22 ,  G06F21/02

Abstract: A device for read protection of at least one area of a non-volatile memory includes an address decoder outputting an addressing signal on one of its output terminals when an the address corresponds to one of the read protected areas of the memory. A state memory is provided for each read protected area to output a state signal indicating whether or not the area is protected in read. A program instructions decoder outputs a program signal indicating whether or not the current addressing operation corresponds to a program instruction. A logic circuit responsive to the addressing signal, the state signal and the program signal outputs an instruction signal to read the read protected area when the program signal indicates that the current addressing operation is applicable to a program instruction.

公开(公告)号：FR2823364A1

公开(公告)日：2002-10-11

申请号：FR0104638

申请日：2001-04-05

Applicant: ST MICROELECTRONICS SA

Inventor： NARCHE PASCAL

IPC: G06F12/14 ,  G06F21/02 ,  G11C16/22 ,  G11C16/26

Abstract: The invention concerns a device for read-protection of at least a zone of a non-volatile storage (10), characterised in that it comprises: an address decoder (40) for supplying on one of the output terminals an addressing signal (NSWHADOW1SEL, NSWHADOWnSEL) when the address corresponds to one of the read-protected zones of the storage (10); a state storage (Mn1, Mn) for each read-protected zone for supplying a state signal (PMPR1, PMPRn) indicating whether the zone is read-protected or not; a programme instruction decoder (DIP) for supplying a programme signal (OP) indicating whether the current addressing operation corresponds or not to a programme instruction; and a logic circuit (42), whereto are applied the addressing signal (NSWHADOW1SEL, NSWHADOWnSEL), the state signal (PMPR1, PMPRn) and the programme signal (OP), for supplying an instruction signal (R10) for reading the read-protected zone when the programme signal (OP) indicates that the current addressing operation concerns a programme instruction.

公开(公告)号：FR2851075B1

公开(公告)日：2005-04-22

申请号：FR0301605

申请日：2003-02-11

Applicant: ST MICROELECTRONICS SA

Inventor： NARCHE PASCAL

IPC: G11C29/02 ,  G11C29/00

公开(公告)号：FR2851075A1

公开(公告)日：2004-08-13

申请号：FR0301605

申请日：2003-02-11

Applicant: ST MICROELECTRONICS SA

Inventor： NARCHE PASCAL

IPC: G11C29/02 ,  G11C29/00

Abstract: The process involves writing words in a memory cell. The written words are highlighted and compared with original words. The memory is cut out into set of cells (ADR:FA00-ADR:FAFF) of which each receives a corresponding set (EM1, EM2, EM6) of different words. Each set of words beyond the set (EM1) is obtained by circular permutation of the set (EM1) of different words.

公开(公告)号：FR2823364B1

公开(公告)日：2003-06-27

申请号：FR0104638

申请日：2001-04-05

Applicant: ST MICROELECTRONICS SA

Inventor： NARCHE PASCAL

IPC: G06F12/14 ,  G06F21/02 ,  G11C16/22 ,  G11C16/26

Abstract: A device for read protection of at least one area of a non-volatile memory includes an address decoder outputting an addressing signal on one of its output terminals when an the address corresponds to one of the read protected areas of the memory. A state memory is provided for each read protected area to output a state signal indicating whether or not the area is protected in read. A program instructions decoder outputs a program signal indicating whether or not the current addressing operation corresponds to a program instruction. A logic circuit responsive to the addressing signal, the state signal and the program signal outputs an instruction signal to read the read protected area when the program signal indicates that the current addressing operation is applicable to a program instruction.