公开(公告)号：FR2928029A1

公开(公告)日：2009-08-28

申请号：FR0851266

申请日：2008-02-27

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

Inventor： BERNARD EMILIE ,  GUILLAUMOT BERNARD ,  CORONEL PHILIPPE

IPC: H01L21/336 ,  H01L29/78

Abstract: L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comportant une région semi-conductrice de canal et une région de grille, la région de grille comprenant au moins une partie enterrée s'étendant sous la région de canal. La formation de la partie enterrée de la région de grille comprend :- une formation d'une cavité sous la région de canal,- un remplissage au moins partiel de la cavité par au moins du silicium et un métal,- la formation d'un siliciure dudit métal.

公开(公告)号：FR2928029B1

公开(公告)日：2011-04-08

申请号：FR0851266

申请日：2008-02-27

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

Inventor： BERNARD EMILIE ,  GUILLAUMOT BERNARD ,  CORONEL PHILIPPE

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：DE69509581D1

公开(公告)日：1999-06-17

申请号：DE69509581

申请日：1995-03-24

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  GUILLAUMOT BERNARD

IPC: H01L21/8247 ,  G11C11/56 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06 ,  G11C16/04

Abstract: The memory cell comprises a p-type channel and gate between an n-type source (12) layer and drain (13) layer with an inner extension (14,15) of lightly doped n-type layer into the gate region. The main isolated gate (GC) is situated over the gate region and the floating gate (GF) is situated over the lightly doped drain region. In charging the cell excess electrons pass to the extension zone and the floating command.

公开(公告)号：DE69509581T2

公开(公告)日：1999-12-23

申请号：DE69509581

申请日：1995-03-24

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  GUILLAUMOT BERNARD

IPC: H01L21/8247 ,  G11C11/56 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06 ,  G11C16/04

Abstract: The memory cell comprises a p-type channel and gate between an n-type source (12) layer and drain (13) layer with an inner extension (14,15) of lightly doped n-type layer into the gate region. The main isolated gate (GC) is situated over the gate region and the floating gate (GF) is situated over the lightly doped drain region. In charging the cell excess electrons pass to the extension zone and the floating command.