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    3.
    发明专利
    未知

    公开(公告)号：FR2795557B1

    公开(公告)日：2001-09-21

    申请号：FR9908240

    申请日：1999-06-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOREL CHRISTOPHE ,  LAVILLE SEBASTIEN ,  PONTAROLLO SERGE

    IPC: H01L21/329 ,  H01L29/8605 ,  H01L29/86 ,  H01C17/22

    Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.

    RESISTANCE INTEGREE DIFFUSEE
    5.
    发明专利
    RESISTANCE INTEGREE DIFFUSEE 未知

    公开(公告)号：FR2918504A1

    公开(公告)日：2009-01-09

    申请号：FR0756321

    申请日：2007-07-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： PONTAROLLO SERGE ,  BERGER DOMINIQUE

    IPC: H01L29/8605 ,  G11C7/06 ,  H01L27/07

    Abstract: L'invention concerne une résistance constituée d'une région faiblement dopée (35) de type P formée dans une partie (29) d'un caisson semiconducteur (25) faiblement dopé de type N s'étendant sur un substrat semiconducteur (21) faiblement dopé de type P, le caisson étant délimité latéralement par un mur de type P (27) s'étendant jusqu'au substrat (21), la partie (29) du caisson (25) étant délimitée verticalement par une zone enterrée fortement dopée de type N (31) à la limite entre le caisson (29) et le substrat (21) et horizontalement par un mur (33) fortement dopé de type N. Une diode (45) est placée entre une borne (37) de la résistance et le mur (33) fortement dopé de type N, la cathode de la diode (45) étant reliée à ladite borne (37).

    6.
    发明专利
    未知

    公开(公告)号：FR2791193B1

    公开(公告)日：2004-07-09

    申请号：FR9903238

    申请日：1999-03-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： PONTAROLLO SERGE

    IPC: H02M3/07

    Abstract: A method is provided for controlling a capacitive charge pump. The charge pump is regulated by a regulating voltage when the supply voltage is greater than the regulating voltage. When the supply voltage is less than a triggering voltage, which is less than or equal to the regulating voltage, the charge pump is automatically supplied between the supply voltage and ground. In one preferred method, the charge pump has a first supply terminal connected to the supply voltage and a second supply terminal that is automatically grounded when the supply voltage is less than the triggering voltage. Also provided is a capacitive charge pump device that includes a charge pump having first and second supply terminals, a voltage regulator delivering a regulating voltage, a switch connected between the second supply terminal and ground, and switch control circuitry for automatically controlling the switch. The first supply terminal is connected to a supply voltage and the voltage regulator is connected between the first and second supply terminals. The switch control circuitry opens the switch when the supply voltage is greater than or equal to a triggering voltage, which is less than the regulating voltage, and closes the switch when the supply voltage is less than the triggering voltage.

    Pulse width modulated signal generation method for power control applications, involves comparison of control signal to reference signal
    7.
    发明专利
    Pulse width modulated signal generation method for power control applications, involves comparison of control signal to reference signal 未知

    公开(公告)号：FR2791198A1

    公开(公告)日：2000-09-22

    申请号：FR9903239

    申请日：1999-03-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： PONTAROLLO SERGE

    IPC: H03K7/08 ,  H03K3/00

    Abstract: The method involves comparison of control signal to reference signal. When the control signal (Vc) is a digital signal with two logic states, it is compared to the first reference voltage (VRef1), and the difference in levels between the control signal and the first reference voltage is made greater than the offset voltage of the comparator (COMP2). When the control signal (Vc) is an analog signal, the sawtooth reference signal varies between the first reference voltage (VRef1) and the second reference voltage (VRef2), which is higher than the first. Then the first reference voltage (VRef1) is generated in the floating manner by connecting the first voltage source (ST1) between the inverted input of the comparator (COMP2) and a capacitor (CF), which is connected to the ground. The control voltage is applied to the non-inverted input of the comparator (COMP2). When the control signal (Vc) is the digital signal, the terminal of the first voltage source (ST1) connected to the capacitor (CF) is joined to ground.

    9.
    发明专利
    未知

    公开(公告)号：FR2855683A1

    公开(公告)日：2004-12-03

    申请号：FR0306344

    申请日：2003-05-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： DULAU LAURENT ,  PONTAROLLO SERGE

    IPC: H03K4/00 ,  H03K17/16 ,  H03K17/687 ,  H03K17/0812

    Abstract: A device for controlling a voltage-controlled switch, including two circuits respectively for setting to the high level and for setting to the low level a control terminal of the voltage-controlled switch, one at least of the circuits including a power transistor capable of connecting the control terminal to a high, respectively low voltage, a bipolar control transistor having its emitter, respectively its collector, connected to the control terminal of the power transistor, the base of the control transistor being likely to receive a control current and a first diode connected between a first predetermined voltage smaller than the high voltage, and the base of the control transistor.

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