公开(公告)号：DE69509606T2

公开(公告)日：1999-12-16

申请号：DE69509606

申请日：1995-08-28

Applicant: ST MICROELECTRONICS SA

Inventor： BERNARD PATRICK ,  BELOT DIDIER ,  QUERVEL JACQUES

IPC: H03K17/62 ,  H03K19/0944 ,  H03K19/00

Abstract: The logic circuit includes a first differential stage (Q1,Q2) constructing using bipolar transistors operating in their linear region. These are mounted in one branch of a second differential stage (M5,M6) biased by a current source (M7). The second stage and the current source are constructed using MOS transistors. The MOS transistors of the second stage receive on their grids the same levels of voltage as the bases of the bipolar transistors of the first stage. The current source transistor (M7) has its source connected direction of the supply voltage (GND).

公开(公告)号：DE69509606D1

公开(公告)日：1999-06-17

申请号：DE69509606

申请日：1995-08-28

Applicant: ST MICROELECTRONICS SA

Inventor： BERNARD PATRICK ,  BELOT DIDIER ,  QUERVEL JACQUES

IPC: H03K17/62 ,  H03K19/0944 ,  H03K19/00

Abstract: The logic circuit includes a first differential stage (Q1,Q2) constructing using bipolar transistors operating in their linear region. These are mounted in one branch of a second differential stage (M5,M6) biased by a current source (M7). The second stage and the current source are constructed using MOS transistors. The MOS transistors of the second stage receive on their grids the same levels of voltage as the bases of the bipolar transistors of the first stage. The current source transistor (M7) has its source connected direction of the supply voltage (GND).