公开(公告)号：DE69715746T2

公开(公告)日：2003-05-22

申请号：DE69715746

申请日：1997-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS ,  LAUR JEAN-PIERRE

IPC: H02H3/02 ,  H02H9/02 ,  H01L27/06

Abstract: Three interconnected transistors are used to limit or cut off current flowing between terminals (A,K). A first transistor (NMOSD1) has it's collector connected to the first terminal (A) and it's base to the second terminal (K). A second complementary transistor (PMOSD) is connected to terminal (K) and the first transistor's emitter. The base of the second transistor is connected to the emitter of a third transistor (NMOSD2) and the third transistor has it's collector connected to terminal (A) and it's base connected to terminal (K). A Zener diode is connected between the emitter and base of the third transistor.

公开(公告)号：DE69715746D1

公开(公告)日：2002-10-31

申请号：DE69715746

申请日：1997-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS ,  LAUR JEAN-PIERRE

IPC: H02H3/02 ,  H02H9/02 ,  H01L27/06

Abstract: Three interconnected transistors are used to limit or cut off current flowing between terminals (A,K). A first transistor (NMOSD1) has it's collector connected to the first terminal (A) and it's base to the second terminal (K). A second complementary transistor (PMOSD) is connected to terminal (K) and the first transistor's emitter. The base of the second transistor is connected to the emitter of a third transistor (NMOSD2) and the third transistor has it's collector connected to terminal (A) and it's base connected to terminal (K). A Zener diode is connected between the emitter and base of the third transistor.

公开(公告)号：DE69722089D1

公开(公告)日：2003-06-26

申请号：DE69722089

申请日：1997-07-24

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE

IPC: H01L27/07 ,  H01L29/74

公开(公告)号：DE69619488D1

公开(公告)日：2002-04-04

申请号：DE69619488

申请日：1996-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  SANCHEZ JEAN-LOUIS ,  JALLADE JEAN

IPC: H02H3/02 ,  H02H9/02

Abstract: The static monolithic current limiter and circuit breaker comprises two terminals (A,K), between which there is a uni-directional current limiter (1), and a detector (2) sensing the voltage between the terminals. A switch device (3) is arranged to inhibit conduction through the current limiter when the detected voltage exceeds a given threshold. The voltage detector is formed by a potential divider (2) connected between the terminals, with its mid-point providing the output indication. This potential divider may be constructed from two MOS transistors with N-type depletion channels connected in series. The current limiter may also be an MOS transistor with an N-type depletion channel of vertical format. Alternatively this limiter may be a vertical IGBT type transistor with a depletion channel, and in yet another configuration may be a bipolar transistor used in conjunction with an N-type depletion MOS transistor.