公开(公告)号：DE69619488D1

公开(公告)日：2002-04-04

申请号：DE69619488

申请日：1996-12-17

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  SANCHEZ JEAN-LOUIS ,  JALLADE JEAN

IPC: H02H3/02 ,  H02H9/02

Abstract: The static monolithic current limiter and circuit breaker comprises two terminals (A,K), between which there is a uni-directional current limiter (1), and a detector (2) sensing the voltage between the terminals. A switch device (3) is arranged to inhibit conduction through the current limiter when the detected voltage exceeds a given threshold. The voltage detector is formed by a potential divider (2) connected between the terminals, with its mid-point providing the output indication. This potential divider may be constructed from two MOS transistors with N-type depletion channels connected in series. The current limiter may also be an MOS transistor with an N-type depletion channel of vertical format. Alternatively this limiter may be a vertical IGBT type transistor with a depletion channel, and in yet another configuration may be a bipolar transistor used in conjunction with an N-type depletion MOS transistor.

公开(公告)号：DE69425397T2

公开(公告)日：2001-03-01

申请号：DE69425397

申请日：1994-05-09

Applicant: ST MICROELECTRONICS SA

Inventor： AYELA CHRISTOPHE ,  LETURCO PHILIPPE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78 ,  H01L29/86 ,  H02H9/02

Abstract: The present invention relates to a current limiting dipole component, comprising a substrate (11) with a first type of conductivity; separate wells (21, 22) with the second type of conductivity; a first annular region (34) with the first type of conductivity in each well; a second annular region (38) with the first type of conductivity having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer (42) on the second annular region and the flush surfaces of the substrate; a first metallisation (44) over the upper surface of the component; and a second metallisation over the lower surface of the component.

公开(公告)号：DE69425397D1

公开(公告)日：2000-09-07

申请号：DE69425397

申请日：1994-05-09

Applicant: ST MICROELECTRONICS SA

Inventor： AYELA CHRISTOPHE ,  LETURCO PHILIPPE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78 ,  H01L29/86 ,  H02H9/02

Abstract: The present invention relates to a current limiting dipole component, comprising a substrate (11) with a first type of conductivity; separate wells (21, 22) with the second type of conductivity; a first annular region (34) with the first type of conductivity in each well; a second annular region (38) with the first type of conductivity having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer (42) on the second annular region and the flush surfaces of the substrate; a first metallisation (44) over the upper surface of the component; and a second metallisation over the lower surface of the component.

公开(公告)号：DE69938814D1

公开(公告)日：2008-07-10

申请号：DE69938814

申请日：1999-12-28

Applicant: ST MICROELECTRONICS SA

Inventor： JALADE JEAN ,  SANCHEZ JEAN-LOUIS ,  LAUR JEAN-PIERRE ,  BREIL MARIE ,  AUSTIN PATRICK ,  BERNIER ERIC ,  ROY MATHIEU

IPC: H01L27/06 ,  H01L29/74 ,  H01L21/822 ,  H01L27/04 ,  H01L29/739 ,  H01L29/78

公开(公告)号：DE69715746T2

公开(公告)日：2003-05-22

申请号：DE69715746

申请日：1997-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS ,  LAUR JEAN-PIERRE

IPC: H02H3/02 ,  H02H9/02 ,  H01L27/06

Abstract: Three interconnected transistors are used to limit or cut off current flowing between terminals (A,K). A first transistor (NMOSD1) has it's collector connected to the first terminal (A) and it's base to the second terminal (K). A second complementary transistor (PMOSD) is connected to terminal (K) and the first transistor's emitter. The base of the second transistor is connected to the emitter of a third transistor (NMOSD2) and the third transistor has it's collector connected to terminal (A) and it's base connected to terminal (K). A Zener diode is connected between the emitter and base of the third transistor.

公开(公告)号：DE69715746D1

公开(公告)日：2002-10-31

申请号：DE69715746

申请日：1997-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： QUOIRIN JEAN-BAPTISTE ,  JALADE JEAN ,  SANCHEZ JEAN-LOUIS ,  LAUR JEAN-PIERRE

IPC: H02H3/02 ,  H02H9/02 ,  H01L27/06

Abstract: Three interconnected transistors are used to limit or cut off current flowing between terminals (A,K). A first transistor (NMOSD1) has it's collector connected to the first terminal (A) and it's base to the second terminal (K). A second complementary transistor (PMOSD) is connected to terminal (K) and the first transistor's emitter. The base of the second transistor is connected to the emitter of a third transistor (NMOSD2) and the third transistor has it's collector connected to terminal (A) and it's base connected to terminal (K). A Zener diode is connected between the emitter and base of the third transistor.