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公开(公告)号：WO0245261A3
公开(公告)日：2003-05-30
申请号：PCT/FR0103788
申请日：2001-11-29
Applicant: ST MICROELECTRONICS SA , MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
Inventor： MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
IPC: H03G7/06
CPC classification number: H03G7/06
Abstract: The invention concerns a controllable set of current sources (6') comprising several output terminals (Si), a first transistor (T1i') associated with each first output terminal, the current (li) on each first output terminal depending on the current passing through the first transistor, and control means (8) designed, in response to a predetermined control voltage variation (VAB), to make each first transistor (T1i') gradually conductive then gradually non-conductive, wherein the first transistors are MOS transistors, and wherein each first output terminal (Si) is associated with a current mirror formed by MOS transistors (T2i, T3i), said current mirror supplying to the first output terminal a current dependent on the current passing through the first transistor.
Abstract translation: 本发明涉及一组可控的电流源（6'），其包括多个输出端子（Si），与每个第一输出端子相关联的第一晶体管（T1i'），每个第一输出端子上的电流（li）取决于电流通过 通过第一晶体管和响应于预定控制电压变化（VAB）而设计的控制装置（8）使得每个第一晶体管（T1i'）逐渐导通，然后逐渐不导电，其中第一晶体管是MOS晶体管， 并且其中每个第一输出端子（Si）与由MOS晶体管（T2i，T3i）形成的电流镜相关联，所述电流镜向第一输出端子提供取决于通过第一晶体管的电流的电流。
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公开(公告)号：WO0249210A3
公开(公告)日：2003-09-18
申请号：PCT/FR0104007
申请日：2001-12-14
Applicant: ST MICROELECTRONICS SA , MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
Inventor： MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
IPC: H03G7/08
CPC classification number: H03G7/08
Abstract: The invention concerns a variable-gain differential input and output amplifier comprising an attenuation network (AT1, AT2), receiving an input voltage (V1in-V2in) and supplying on several outputs (O1i, O2i) voltages each of which is equal to the attenuated input voltage; differential transconductance elements (G1i, G2i) each having a first input connected to an output (O1i, O2i) of the attenuation network, and producing first (l ) and second (l +) positive currents and first (1 ) and second (1 ) negative currents, a set of current sources (10) for controlling transconductance of each transconductance element based on an analog control signal (Vcom); and an output block (26) converting the first and second input currents into a differential output voltage (V1out-V2out) and supplying to the second input of each transconductance element a feedback voltage dependent on the output voltage.
Abstract translation: 本发明涉及一种可变增益差分输入和输出放大器，包括衰减网络（AT1，AT2），接收输入电压（V1in-V2in）并提供多个输出（O1i，O2i）电压，每个电压等于衰减 输入电压; 每个差分跨导元件（G1i，G2i）具有连接到衰减网络的输出（O1i，O2i）的第一输入，并且产生第一（1 + 1 + 1）和第二（1 + （1 <1->）和第二（1 <2->）负电流，用于基于模拟控制信号（Vcom）控制每个跨导元件的跨导的一组电流源（10）; 以及将所述第一和第二输入电流转换为差分输出电压（V1out-V2out）并将每个跨导元件的第二输入端提供给依赖于所述输出电压的反馈电压的输出块（26）。
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公开(公告)号：FR2850499B1
公开(公告)日：2005-10-21
申请号：FR0300933
申请日：2003-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： RAVATIN JEAN , VAN ZANTEN FRANCOIS
Abstract: The circuit for correcting the offset of a chain (2) for amplification and low-pass filtering having a predetermined gain (G) and cut-off frequency (Fc) depending on the value of at least one capacitor, comprises a digital-analog converter (18) for the return of a correction signal (delta) dependent on the value of a programmable digital word (COM), a digital automaton (14) for finding and storing one of two consecutive values of the digital word between which the output signal changes sign so that the input signal is annulled during an adjustment phase, and tuning elements (22,24) for reducing the value of at least one capacitor with respect to its normal functioning value. The circuit with a determined cut-off frequency (Fc) dependent on several capacitors comprises means for reducing the value of each capacitance during the tuning phase. The means for reducing the value of at least one capacitance consist of means for switching at least one capacitor with another of lower capacitance, or at least one capacitor is formed of a low-value capacitance connected in parallel with a set of small capacitors each in series with a programmable switch. The method (claimed) for correcting the offset of a chain for amplification and low-pass filtering, comprises the steps of annulling the input signal, returning a correction signal dependent on the value of a digital word and modifying the value until the output signal changes sign, and storing the value of the digital word.
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公开(公告)号：FR2833429A1
公开(公告)日：2003-06-13
申请号：FR0115755
申请日：2001-12-06
Applicant: ST MICROELECTRONICS SA
Inventor： GIRY CASSAN FLORENCE , VAN ZANTEN FRANCOIS
Abstract: The method comprises the measuring of the power of the digital signal by the first measuring means (MM1) after an analogue-digital conversion (CAN) and the controlling of the gain on the basis of the measured power according to a predetermined law by the control means (MC) connected to the amplifiers control logic (ACTL) for controlling the gains (G1,G2) of two amplifiers with gain control (AGC1,AGC2) in the main branch of the tuner (TN). The method also comprises the measuring of the power of the analogue signal by the second measuring means (MM2) picked up between the input amplifier stage (AGC1) and the first stage of frequency transposition, that is the first mixer (MX1), or immediately after the mixer, the comparing of the measured power to a predetermined power threshold (SSE) in a manner to obtain the first binary information, and the adjusting of the law for controlling the gain on the basis of binary control values obtained from the first binary information by a bistable (BSC) connected to a filter (FN). If the measured power is greater than the threshold value (SSE), the law of control is modified, and in other cases it is left unchanged. The tuner (TN) is of the double-conversion type and comprises the second-stage transposition or mixing (MX2) connected downstream of the first-stage transposition or mixing (MX1), and two stages of amplification (AGC1,AGC2), where the law of the gain control comprises the first adjustment of gain (G1) of the input amplification stage and the second adjustment of gain (G2) of the second amplification stage. The modification of the law of control comprises a supplementary decrease of the gain (G1) and an increase of the gain (G2). The analogue block (BAN) comprises the amplifiers with gain control (AGC1,AGC2) and two stages of frequency transposition or mixing (MX1,MX2), and is connected to the digital block (BNM) by the analogue-digital conversion stage (CAN). The analogue block also comprises a comparator (CMP) for comparing the measured power with the threshold value (SSE) and delivers the first binary information. The comparator (CMP) functions on the basis of hysteresis. A receiver of terrestrial digital signals is claimed and comprises the tuner as specified.
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公开(公告)号：FR2832579A1
公开(公告)日：2003-05-23
申请号：FR0114921
申请日：2001-11-19
Applicant: ST MICROELECTRONICS SA
Inventor： VAN ZANTEN FRANCOIS , SABUT MARC , RIBAS RAYMOND
Abstract: A video input stage calibration circuit has a differential output stage with variable gain (206) and inverter (106) operational amplifiers creating out of phase voltages about the common level as input to the analogue to digital converter (207) and digital control (260). Includes an Independent claim for the use of Miller gain stages in CMOS (Complementary Metal Oxide Silicon) and PMOS (P Metal Oxide Silicon) technology in the differential converter.
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Patent Agency Ranking
公开(公告)号：FR2818466B1
公开(公告)日：2003-04-04
申请号：FR0016400
申请日：2000-12-15
Applicant: ST MICROELECTRONICS SA
Inventor： MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.
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公开(公告)号：DE69709029D1
公开(公告)日：2002-01-24
申请号：DE69709029
申请日：1997-10-24
Applicant: ST MICROELECTRONICS SA
Inventor： GENS MARC , VAN ZANTEN FRANCOIS
IPC: G05F1/59
Abstract: The voltage regulator delivers a controlled output voltage via MOSFET power transistors (M10M, M10L), with the output voltage set relative to a reference potential (VBG). The regulator has two input terminals (EM, EL), each connected to an independent supply source (VM, VL). An automatic selection circuit (11) connects the higher of the input voltages to the regulator input. The terminal connected to the lower supply voltage is automatically isolated from the remainder of the circuit. The selector (11) introduces a small voltage drop, equal to the voltage drop over a single power transistor, between the input and the output of the regulator.
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公开(公告)号：FR2833429B1
公开(公告)日：2004-07-02
申请号：FR0115755
申请日：2001-12-06
Applicant: ST MICROELECTRONICS SA
Inventor： GIRY CASSAN FLORENCE , VAN ZANTEN FRANCOIS
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公开(公告)号：FR2832519B1
公开(公告)日：2004-02-20
申请号：FR0114926
申请日：2001-11-19
Applicant: ST MICROELECTRONICS SA
Inventor： VAN ZANTEN FRANCOIS , SABUT MARC , RIBAS RAYMOND
Abstract: A mirroring circuit operating at high frequencies is provided. The mirroring circuit includes a first branch having a first transistor in series with a first resistor, a second branch having a second transistor in series with a second resistor, and a servo circuit for controlling current flowing in the first branch and the second branch. The servo circuit includes a third transistor configured as a diode, a source of the third transistor coupled to a source of the first transistor, a fourth transistor configured as a shift lever, a source of the fourth transistor coupled to ground via a third resistor, a fifth transistor configured as a diode, a source of the fifth transistor coupled to a source of the second transistor, and a sixth transistor configured as a shift lever, a source of the sixth transistor coupled to ground via the third resistor.
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公开(公告)号：FR2817408B1
公开(公告)日：2003-03-21
申请号：FR0015522
申请日：2000-11-30
Applicant: ST MICROELECTRONICS SA
Inventor： MOURET MICHEL , SABUT MARC , VAN ZANTEN FRANCOIS
Abstract: A controllable assembly of current sources includes several first output terminals, with a first transistor associated with each first output terminal, the current on each first output terminal depending on the current flowing through the first transistor, and a circuit configured, in response to a predetermined variation of a control voltage, to successively progressively turn on, then progressively turn off, each first transistor. The first transistors are MOS transistors, and each first output terminal is associated with a current mirror formed of MOS transistors, the current mirror providing to the first output terminal a current depending on the current flowing through the first transistor.
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