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    CONTROLLABLE SET OF CURRENT SOURCES
    1.
    发明申请
    CONTROLLABLE SET OF CURRENT SOURCES 审中-公开
    可控电流源

    公开(公告)号：WO0245261A3

    公开(公告)日：2003-05-30

    申请号：PCT/FR0103788

    申请日：2001-11-29

    Applicant: ST MICROELECTRONICS SA ,  MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    Inventor： MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    IPC: H03G7/06

    CPC classification number: H03G7/06

    Abstract: The invention concerns a controllable set of current sources (6') comprising several output terminals (Si), a first transistor (T1i') associated with each first output terminal, the current (li) on each first output terminal depending on the current passing through the first transistor, and control means (8) designed, in response to a predetermined control voltage variation (VAB), to make each first transistor (T1i') gradually conductive then gradually non-conductive, wherein the first transistors are MOS transistors, and wherein each first output terminal (Si) is associated with a current mirror formed by MOS transistors (T2i, T3i), said current mirror supplying to the first output terminal a current dependent on the current passing through the first transistor.

    Abstract translation: 本发明涉及一组可控的电流源（6'），其包括多个输出端子（Si），与每个第一输出端子相关联的第一晶体管（T1i'），每个第一输出端子上的电流（li）取决于电流通过 通过第一晶体管和响应于预定控制电压变化（VAB）而设计的控制装置（8）使得每个第一晶体管（T1i'）逐渐导通，然后逐渐不导电，其中第一晶体管是MOS晶体管， 并且其中每个第一输出端子（Si）与由MOS晶体管（T2i，T3i）形成的电流镜相关联，所述电流镜向第一输出端子提供取决于通过第一晶体管的电流的电流。

    VARIABLE-GAIN DIFFERENTIAL INPUT AND OUTPUT AMPLIFIER
    2.
    发明申请
    VARIABLE-GAIN DIFFERENTIAL INPUT AND OUTPUT AMPLIFIER 审中-公开
    可变增益差分输入和输出放大器

    公开(公告)号：WO0249210A3

    公开(公告)日：2003-09-18

    申请号：PCT/FR0104007

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SA ,  MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    Inventor： MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    IPC: H03G7/08

    CPC classification number: H03G7/08

    Abstract: The invention concerns a variable-gain differential input and output amplifier comprising an attenuation network (AT1, AT2), receiving an input voltage (V1in-V2in) and supplying on several outputs (O1i, O2i) voltages each of which is equal to the attenuated input voltage; differential transconductance elements (G1i, G2i) each having a first input connected to an output (O1i, O2i) of the attenuation network, and producing first (l ) and second (l +) positive currents and first (1 ) and second (1 ) negative currents, a set of current sources (10) for controlling transconductance of each transconductance element based on an analog control signal (Vcom); and an output block (26) converting the first and second input currents into a differential output voltage (V1out-V2out) and supplying to the second input of each transconductance element a feedback voltage dependent on the output voltage.

    Abstract translation: 本发明涉及一种可变增益差分输入和输出放大器，包括衰减网络（AT1，AT2），接收输入电压（V1in-V2in）并提供多个输出（O1i，O2i）电压，每个电压等于衰减 输入电压; 每个差分跨导元件（G1i，G2i）具有连接到衰减网络的输出（O1i，O2i）的第一输入，并且产生第一（1 + 1 + 1）和第二（1 + （1 <1->）和第二（1 <2->）负电流，用于基于模拟控制信号（Vcom）控制每个跨导元件的跨导的一组电流源（10）; 以及将所述第一和第二输入电流转换为差分输出电压（V1out-V2out）并将每个跨导元件的第二输入端提供给依赖于所述输出电压的反馈电压的输出块（26）。

    REGULATEUR DE TENSION A BOUCLE AUTO-ADAPTATIVE
    4.
    发明专利
    REGULATEUR DE TENSION A BOUCLE AUTO-ADAPTATIVE 未知

    公开(公告)号：FR2925184A1

    公开(公告)日：2009-06-19

    申请号：FR0759908

    申请日：2007-12-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： BLISSON FABRICE ,  MORO JEAN LUC ,  SABUT MARC

    IPC: G05F1/575

    Abstract: L'invention concerne un régulateur de tension comprenant un amplificateur (12) et une boucle de régulation comprenant .un premier transistor PMOS (Mpow) connecté à une borne (2) d'alimentation d'entrée (Vin),un deuxième transistor PMOS (P1), monté en série avec le premier transistor PMOS (Mpow), leur point milieu définissant la borne (S) de sortie fournissant la tension de sortie (Vout),une première source d'un premier courant de polarisation (Ib) de valeur fixe relié à la grille du premier transistor (Mpow),une deuxième source d'un deuxième courant de polarisation (2Ib) de valeur fixe reliant le deuxième transistor (P1) à la masse (3), etun troisième transistor NMOS (NCAS) reliant les deux sources de courant (Ib, 2Ib).Selon l'invention, le régulateur comprend en outre des moyens pour modifier automatiquement au moins l'un des courants de polarisation (Ib, 2Ib) en fonction du courant de charge (IL).

    DISPOSITIF DE MEMOIRE DE TYPE SRAM
    5.
    发明专利
    DISPOSITIF DE MEMOIRE DE TYPE SRAM 未知

    公开(公告)号：FR2910168A1

    公开(公告)日：2008-06-20

    申请号：FR0610939

    申请日：2006-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： BARASINSKI SEBASTIEN ,  JACQUET FRANCOIS ,  SABUT MARC

    IPC: G11C11/41 ,  G11C7/12

    Abstract: L'invention concerne un dispositif de mémoire de type SRAM, comprenant un plan mémoire (MEM) constitué de cellules mémoire de base (CELL) organisées en lignes (WLi) et en colonnes (COLj), chaque cellule d'une colonne étant connectée entre deux lignes de bit (BLT, BLF) destinée à être préchargée lors d'une opération de lecture, ledit dispositif: étant caractérisé en ce qu'il comprend des moyens (CELLm) de génération d'une tension de précharge (VBL) des lignes de bit inférieure à une tension d'alimentation nominale (Vdd) dudit dispositif.

    6.
    发明专利
    未知

    公开(公告)号：FR2910168B1

    公开(公告)日：2009-03-20

    申请号：FR0610939

    申请日：2006-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： BARASINSKI SEBASTIEN ,  JACQUET FRANCOIS ,  SABUT MARC

    IPC: G11C11/41 ,  G11C7/12

    Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

    7.
    发明专利
    未知

    公开(公告)号：FR2832579A1

    公开(公告)日：2003-05-23

    申请号：FR0114921

    申请日：2001-11-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： VAN ZANTEN FRANCOIS ,  SABUT MARC ,  RIBAS RAYMOND

    IPC: H04N5/18 ,  H04N5/44

    Abstract: A video input stage calibration circuit has a differential output stage with variable gain (206) and inverter (106) operational amplifiers creating out of phase voltages about the common level as input to the analogue to digital converter (207) and digital control (260). Includes an Independent claim for the use of Miller gain stages in CMOS (Complementary Metal Oxide Silicon) and PMOS (P Metal Oxide Silicon) technology in the differential converter.

    8.
    发明专利
    未知

    公开(公告)号：FR2818466B1

    公开(公告)日：2003-04-04

    申请号：FR0016400

    申请日：2000-12-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

    IPC: H03G7/08 ,  H03G7/06 ,  H03G3/00 ,  H03F1/42 ,  H03F1/32

    Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

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