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    Integrated semiconductor memory device and manufacturing method therefor
    2.
    发明专利
    Integrated semiconductor memory device and manufacturing method therefor 审中-公开
    集成半导体存储器件及其制造方法

    公开(公告)号：JP2003060095A

    公开(公告)日：2003-02-28

    申请号：JP2002178046

    申请日：2002-06-19

    Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

    Inventor： SKOTNICKI THOMAS ,  VILLARET ALEXANDRE

    IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/42336 ,  H01L29/788

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory device having hybrid performance. SOLUTION: The integrated semiconductor memory device is provided with an integrated memory structure CH2 provided with a semiconductor layer surrounded by an isolation layer, lying between the source region S and the drain region D of a transistor and inserted between the channel region of the transistor and its control gate. The semiconductor layer included two potential well zones Z1 and Z3 separated by a potential barrier zone Z2 lying beneath the control gate of the transistor. Write means Vg and Vds bias the memory structure so as to confine charge carriers selectively in one or other of the two potential well zones, and read means Vg and Vd bias the memory structure so as to detect, for example by measuring the drain current of the transistor, the presence of charge carriers in one or other of the potential wells.

    Abstract translation: 要解决的问题：提供具有混合性能的集成半导体存储器件。 解决方案：集成半导体存储器件设置有集成存储器结构CH2，其设置有由隔离层围绕的半导体层，该隔离层位于晶体管的源极区域S和漏极区域D之间，并且插入在晶体管的沟道区域和晶体管的沟道区域之间 其控制门。 半导体层包括由位于晶体管的控制栅极下方的势垒区Z2分开的两个势阱区Z1和Z3。 写装置Vg和Vds偏置存储器结构，以便将电荷载流子选择性地限制在两个势阱区域中的一个或另一个中，并且读装置Vg和Vd偏置存储器结构，以便例如通过测量漏极电流 晶体管，在一个或另一个势阱中存在电荷载体。

    5.
    发明专利
    未知

    公开(公告)号：FR2826180B1

    公开(公告)日：2003-09-19

    申请号：FR0108051

    申请日：2001-06-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOINICKI THOMAS ,  VILLARET ALEXANDRE

    IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239 ,  G11C16/06

    Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

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