公开(公告)号：DE69907600D1

公开(公告)日：2003-06-12

申请号：DE69907600

申请日：1999-10-21

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： JAOUEN HERVE ,  FERRANT RICHARD

IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: The cell memory of dynamic random access type comprises a MOS (metal-oxide-silicon) transistor and a capacitor in monolithic structure with the second electrode (311) common to all cells of the same row covered with an insulating layer (312), and comprising independent conducting elements (313-1,313-2) mutually spaced in the same horizontal plane and alternatively high and low polarized. The low potential is the reference potential of the memory circuit equal to e.g. that of the ground. The high potential is the writing potential equal to e.g. the supply potential Vdd. The second electrode (311) is made up of a metallic layer of e.g. tungsten, and a conducting layer of e.g. polycrystalline silicon. The insulating layer (312) is of e.g. silicon oxide. The equivalent capacitance of the memory circuit is in the form of three decoupling capacitors connected in a triangle; the first and second capacitors are formed between the second electrode (311) and the first and the second conducting elements, respectively; the third capacitor is formed between the first and the second elements (313-1) and (313-2). In the case of the conducting elements with a surface of size 1.55 micrometer by 2.8 micrometer, and the insulating layer of thickness 9 micrometer, the three capacitances are: 145 pF, 166 pF, and 166 pF.

公开(公告)号：JP2000133789A

公开(公告)日：2000-05-12

申请号：JP29380599

申请日：1999-10-15

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  FERRANT RICHARD

IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM with which a power source and a ground are protected from charging variation of a memory element. SOLUTION: Cells 1-n of a memory circuit construction include MOS transistors M1-Mn and capacitors C1-Cn. An electrode 311 is connected in common to all cells of the same line and is covered with an insulator 312. The insulator is covered with independent conductive elements 313-1 and 313-2 which are diffused on the same horizontal plane. The two adjacent elements 313-1 and 313-2 are respectively biased at a high potential or a low potential. The low potential is a reference potential of the circuit, in which the cells are formed. The high potential is a potential Vdd for writing in the memory cells.

公开(公告)号：JP2002042481A

公开(公告)日：2002-02-08

申请号：JP2001196763

申请日：2001-06-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a row constituting of spare memory cells which is realized more simply and more effectively in a memory circuit, and to provide a circuit in which the occupied surface area is smaller than a conventional circuit having spare cells. SOLUTION: This dynamic memory circuit includes memory cells arranged in rows and columns, each row which can be started by a word line, each column fomed by cells connected to first and second bit lines, at least one spare row formed by static memory cells being coped so as to be started to replace a memory cell row, and each spare cell connected to the first and the second bit lines of a column of a circuit.

公开(公告)号：WO0249034A2

公开(公告)日：2002-06-20

申请号：PCT/FR0104004

申请日：2001-12-14

Applicant: ST MICROELECTRONICS SA ,  FERRANT RICHARD

Inventor： FERRANT RICHARD

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/1006

Abstract: The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

Abstract translation: 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

公开(公告)号：DE69835784D1

公开(公告)日：2006-10-19

申请号：DE69835784

申请日：1998-03-03

Applicant: ST MICROELECTRONICS SA

Inventor： KALNITSKY ALEXANDER ,  FERRANT RICHARD

IPC: H01L21/768 ,  H03K3/356 ,  H01L21/82 ,  H01L23/525 ,  H01L27/11

公开(公告)号：FR2794301B1

公开(公告)日：2004-10-08

申请号：FR9906797

申请日：1999-05-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS

IPC: H02M3/07

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

公开(公告)号：DE60102037D1

公开(公告)日：2004-03-25

申请号：DE60102037

申请日：2001-06-14

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/4094

公开(公告)号：DE60002403T2

公开(公告)日：2004-03-25

申请号：DE60002403

申请日：2000-07-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: H03K3/012 ,  H03K3/03

Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).

公开(公告)号：DE60100581D1

公开(公告)日：2003-09-18

申请号：DE60100581

申请日：2001-06-29

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

公开(公告)号：DE60002403D1

公开(公告)日：2003-06-05

申请号：DE60002403

申请日：2000-07-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: H03K3/012 ,  H03K3/03

Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).