公开(公告)号：JP2002258903A

公开(公告)日：2002-09-13

申请号：JP2001396005

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBISSO SALVATORE ,  CAPONETTO RICCARDO ,  DIAMANTE OLGA ,  PORTO DOMENICO ,  DI COLA EUSEBIO ,  FORTUNA LUIGI

IPC: G06N3/00 ,  G05B11/42 ,  G05B13/02

Abstract: PROBLEM TO BE SOLVED: To provide a circuit adapted for realizing a non-integral order dynamic system. SOLUTION: In this circuit for realizing a non-integral order dynamic system including a neural network(1-5) adapted for generating at least one output signal(OS) by receiving at least one input signal(IS), the input signal and output signal are related with each other in a non-integral order differential/integral relation based on the coefficients of the neutral network (1-5). A plurality of circuits (I, II) for realizing a non-integral order (PI D ) controller are connected to each other, and a signal is generated by either an integrating block (200) or a differentiating block (202) included in those circuits, and the signal is supplied to the integrating block (200) or the differentiating block (202) of the other circuit in this system.

公开(公告)号：DE602006018259D1

公开(公告)日：2010-12-30

申请号：DE602006018259

申请日：2006-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： NASTASI GIUSEPPE ,  ABBISSO SALVATORE ,  ORTISI VINCENZO

IPC: H01M8/04 ,  H01M8/10 ,  H01M8/12

公开(公告)号：IT201900003331A1

公开(公告)日：2020-09-07

申请号：IT201900003331

申请日：2019-03-07

Applicant: ST MICROELECTRONICS SRL

Inventor： TORRISI GIOVANNI LUCA ,  ABBISSO SALVATORE ,  MERONI CRISTIANO

IPC: G05F20060101

公开(公告)号：IT201800009272A1

公开(公告)日：2020-04-09

申请号：IT201800009272

申请日：2018-10-09

Applicant: ST MICROELECTRONICS SRL

Inventor： TORRISI GIOVANNI LUCA ,  ABBISSO SALVATORE ,  MERONI CRISTIANO

IPC: H02H20060101

公开(公告)号：ITMI20070100A1

公开(公告)日：2008-07-25

申请号：ITMI20070100

申请日：2007-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBISSO SALVATORE ,  CALIGIORE CLAUDIA ,  LEONARDI SALVATORE ,  MADDIONA LIDIA ,  NASTASI GIUSEPPE ANTONIO MARIA

公开(公告)号：DE60018587D1

公开(公告)日：2005-04-14

申请号：DE60018587

申请日：2000-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBISSO SALVATORE ,  CAPONETTO RICCARDO ,  DIAMANTE OLGA ,  PORTO DOMENICO ,  DI COLA EUSEBIO ,  FORTUNA LUIGI

IPC: G06N3/00 ,  G05B11/42 ,  G05B13/02

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network (1 to 5) adapted to receive at least one input signal (IS) and to generate therefrom at least one output signal (OS). The input and output signals (IS, OS) are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network (1 to 5). A plurality (I, II) of such circuits, implementing respective non-integer order (PI D ) controllers can be interconnected in an arrangement wherein any of the integral (200) or differential (202) blocks included in one of those circuits generates a signal which is fed to any of the integral (200) or differential (204) blocks of another circuit in the system.