-
公开(公告)号:JP2002189026A
公开(公告)日:2002-07-05
申请号:JP2001252501
申请日:2001-08-23
Applicant: ST MICROELECTRONICS SRL
Inventor: ARENA PAOLO , FORTUNA LUIGI , LAVORGNA MARIO , OCCHIPINTI LUIGI
IPC: G01N33/53 , C12M1/00 , C12N15/09 , G01N33/566 , G01N37/00 , G06F19/00 , G06K9/00 , G06T1/00 , G06T7/00 , G06T11/60
Abstract: PROBLEM TO BE SOLVED: To solve the problem of even though images can be processed simultaneously with a microarray in parallel in a microarray technique, the processing speed of an analytical technique using a digital microprocessor is limited and the efficiency of the technique is disturbed. SOLUTION: The system, by which an image containing the matrix of spots, such as the images or the like of a hybridized DNA microarrays after hybridization has been conducted, is provided. The system is provided with a circuit 20 which processes an image signal corresponding to the images. The circuit is constituted on the basis of the architecture of a cellular neural network(CNN) for the parallel analog processing of the image signal. The circuit can be related to a sensor 10 acquiring the images, and it can be integrated with a single monolithic component, on which a VLSI CMOS technique is mounted.
-
公开(公告)号:JP2002258903A
公开(公告)日:2002-09-13
申请号:JP2001396005
申请日:2001-12-27
Applicant: ST MICROELECTRONICS SRL
Inventor: ABBISSO SALVATORE , CAPONETTO RICCARDO , DIAMANTE OLGA , PORTO DOMENICO , DI COLA EUSEBIO , FORTUNA LUIGI
Abstract: PROBLEM TO BE SOLVED: To provide a circuit adapted for realizing a non-integral order dynamic system. SOLUTION: In this circuit for realizing a non-integral order dynamic system including a neural network(1-5) adapted for generating at least one output signal(OS) by receiving at least one input signal(IS), the input signal and output signal are related with each other in a non-integral order differential/integral relation based on the coefficients of the neutral network (1-5). A plurality of circuits (I, II) for realizing a non-integral order (PI D ) controller are connected to each other, and a signal is generated by either an integrating block (200) or a differentiating block (202) included in those circuits, and the signal is supplied to the integrating block (200) or the differentiating block (202) of the other circuit in this system.
-
公开(公告)号:JP2000138668A
公开(公告)日:2000-05-16
申请号:JP28864699
申请日:1999-10-08
Applicant: ST MICROELECTRONICS SRL
Inventor: ITALIA FRANSCECO , FORTUNA LUIGI , BERITELLI FRANCESCO , DI COLA EUSEBIO
Abstract: PROBLEM TO BE SOLVED: To enhance a security level in an encipherment system based on a digital chaos model. SOLUTION: The processing is started from a couple of password codes or user keys, a discrete chaos model or map having a couple of the password codes or user keys is generated, a couple of the updated password codes or keys are dynamically generated for each processing step of a certain number in the chaos map, data to be transmitted in a transmission station are masked through logical combination with the dynamically updated keys at present, and a reception station eliminates the mask from the data by separating logically the digital data from the dynamically updated keys at present to restore the digital data in a clear state.
-
公开(公告)号:DE60107529D1
公开(公告)日:2005-01-05
申请号:DE60107529
申请日:2001-01-12
Applicant: ST MICROELECTRONICS SRL
Inventor: OCCHIPINTI LUIGI , FORTUNA LUIGI , RIZZO ALESSANDRO , FRASCA MATTIA
IPC: H04L27/00
Abstract: A chaotic-signal generator comprises a set of elements (1 to 4) for generating signals, which are connected together according to a scheme of chaotic dynamics of signal generation. The connection scheme may advantageously correspond to the circuit generally referred to as Chua's circuit, in particular in its possible implementation as a cellular neural network (CNN). Interposed in the aforementioned connection scheme is at least one switch (5), such as a MOS transistor, the opening and closing of which causes the variation in the chaotic dynamics of signal generation. The opening and closing command signal (u(t)) applied to the aforesaid switch (5) may therefore be made to correspond to a modulating signal in view of transmission on a channel, such as a high-noise channel. In a particularly preferred application, the aforementioned modulating signal is a binary signal, and the aforementioned opening and closing command signal is constituted by a switching signal, the switching frequency of which is caused respectively to increase or decrease depending on the logic level assumed by the modulating signal.
-
公开(公告)号:IT201900010269A1
公开(公告)日:2020-12-27
申请号:IT201900010269
申请日:2019-06-27
Applicant: ST MICROELECTRONICS SRL
Inventor: BRANCIFORTE MARCO MARIA , FORTUNA LUIGI , BUSCARINO ARTURO , BUCOLO MAIDE , PORUTHOTAGE FERNANDO NUWAN
IPC: H02J20060101
-
公开(公告)号:DE69835750D1
公开(公告)日:2006-10-12
申请号:DE69835750
申请日:1998-10-30
Applicant: ST MICROELECTRONICS SRL
Inventor: ARENA PAOLO , CAPONETO RICCARDO , FORTUNA LUIGI , OCCHIPINTI LUIGI
IPC: B25J9/16 , B62D57/032
-
公开(公告)号:DE69828401D1
公开(公告)日:2005-02-03
申请号:DE69828401
申请日:1998-10-12
Applicant: ST MICROELECTRONICS SRL
Inventor: ITALIA FRANCESCO , FORTUNA LUIGI , BERITELLI FRANCESCO , DI COLA EUSEBIO
Abstract: A cryptation system for information transmitted through packet switching networks including masking the digital information data by combining them at the transmitting station with digital data of a certain code of cryptation before transmitting the so encrypted data through the network and performing an inverse decrypting processing at the receiving station using the same code of encrypting, comprises generating at a transmitting station and at a receiving station, starting from a given pair of password codes or user key, a certain discrete chaotic model or map of said pair of codes or key, producing dynamically updated pairs of values of codes or keys every certain number of processing steps of said chaotic map, masking the data to be transmitted by way of a logic combination with said current dynamically updated keys at the transmitting station, demasking the data at the receiving station by way of a logic decomposition of said digital data from said current dynamically updated key returning the digital data to a clear condition.
-
公开(公告)号:ITVA20080062A1
公开(公告)日:2010-06-16
申请号:ITVA20080062
申请日:2008-12-15
Applicant: ST MICROELECTRONICS SRL
-
公开(公告)号:DE60139793D1
公开(公告)日:2009-10-15
申请号:DE60139793
申请日:2001-12-21
Applicant: ST MICROELECTRONICS SRL
Inventor: FORTUNA LUIGI , RIZZO ALESSANDRO , FRASCA MATTIA , BRANCIFORTE MARCO , BARTOLONE MARCO
Abstract: A system for detecting distances, usable, for instance, in the vehicle sector or in robotics applications, comprises at least one transducer (16), such as a piezoelectric transducer, for generating a transmission signal to be sent in the direction of an obstacle (O) and for obtaining a receiving signal corresponding to an echo produced by the reflection of said transmission signal off the obstacle (O). The transducer (16) is driven by a chaos generator (10), such as a Chua's circuit (10). The system preferably comprises a correlator (18) for correlating the transmission signal (TX) and the receiving signal (RX) so that the distance between the obstacle and the transducer (16) is identified by the instant at which the aforesaid correlation assumes the maximum value. Preferably, the transmission signal (TX) is a square-wave signal selectively generated with one first frequency and one second frequency, the jumps between said two frequencies being determined by the instants of emission of the pulses (CPPM) generated by a pulse generator of an analog type (12) driven by the chaos generator (10).
-
公开(公告)号:DE60034562T2
公开(公告)日:2008-01-17
申请号:DE60034562
申请日:2000-08-25
Applicant: ST MICROELECTRONICS SRL
Inventor: ARENA PAOLO UNI D STUD , FORTUNA LUIGI , LAVORGNA MARIO , OCCHIPINTI LUIGI
IPC: G01N33/53 , G06T7/00 , C12M1/00 , C12N15/09 , G01N33/566 , G01N37/00 , G06F19/00 , G06K9/00 , G06T1/00 , G06T11/60
Abstract: The system can be used for the automatic analysis of images (I), comprising a matrix of spots, such as images of DNA microarrays after hybridisation. The system can be associated - and preferably integrated in a single monolithic component implementing VLSI CMOS technology - to a sensor (10) for acquiring said images (I). The system comprises a circuit (20) for processing the signals corresponding to the images (I), configured according to a cellular neural network (CNN) architecture for the parallel analogue processing of signals.
-
-
-
-
-
-
-
-
-